Design of Alu-Based Symmetric Transparent Online BIST for RAM

Authors

  • V. Rajendra Chary   Department of Electronics and Communication Engineering, Sreenidhi Institute of Science and Technology, Affiliated to Jawaharlal Nehru Technological University, Hyderabad, Telangana, India

Keywords:

RAM, Signature Prediction, Test Pattern

Abstract

A 3-bit RAM is tested using 5-bit ALU with the help of symmetric transparent online BIST scheme. This architecture skips signature prediction. It also reduces test time. If the RAM output consists if all 1’s, then it indicates that there is no error in the RAM module, otherwise it indicates that there is an error. The implemented scheme utilizes an ALU in order to generate the test pattern and compress the responses of the memory module, the word width of memory can be smaller than the number of stages of ALU. Hence multiple non-identical memories can also be tested in a pipeline way. All synthesis and simulation results are performed using xilinx14.2 ISE

References

  1. Voyiatzis, C. Efstathiou, C. "Symmetric Transparent Online BIST forArraysof Word-OrganizedRAMs", IEEE 2013
  2. R. Aikten,et.al, "A Modular Wrapper enabling high speed BIST and repair for small wide memories"proc.of Int. Test conference,pp.997-1005,2004
  3. X.Du,N.Mukherjee,W.T. Cheng and S.M.Reddy, " Full speed field programmable memory BIST architecture". proc.of Int. Test conference,pp.1173-1182,2005
  4. A.J.Vande Goor, "Using March Tests to test SRAMs",IEEE design and test of computers,1993
  5. K.Thaller and A.Steininger, " A transparent online memory test for simultaneous detection of functional faults and soft erros in memories," IEEE trans.pp 413-422,2003
  6. Jin-Fu Li, "Transparent test methodologies for RAM with/without ECC" CAD of Integrated Circuits and Systems,IEEE,pp 1888-1893,vol 26,issue 10,2007
  7. M.Nicolaidis, "Theory of transparent BIST for RAMs."IEEE trans on computers,vol.45,no-10,pp1141-1156,1996
  8. M.Nicolaidis, "An efficient BIST for functional test of embedded RAMs"15th symposium on fault tolerant computing,1985.
  9. V. N. Yarmolik, S. Hellebrand. H.-J. Wunderlich, "Symmetric Transparent BIST for RAMs",1999.
  10. V.N. Yarmolik., I.V. Bykov, S. Hellebrand, 11.-i. Wunderlich, Transparent Word-Oriented Memory BIST based on Symmetric March Algorithms", in European Dependable Computing Conference, 1999.
  11. I.Voyiatzis, "Accumulator based compression on Symmetric transparent RAM BIST" IEEE International conference on design and technology of Integrated Systems in Nanoscale technology,2006
  12. M.Psarakis, D.Gizopoulos,M.Sonza Reorda, "Microprocessors software based self testing"IEEE design and test of computers magazine,vol 27,no.3,pp 4-19,2010
  13. Ioannis Voyiatzis, "An Accumulator- Based Compaction Scheme for online BIST of RAMs". IEEE xplore 2009
  14. Paul McEvoy and Ronan Farrel, "Built-in test engine for memory test", IEEE IC Test Workshop, Sep 2004.
  15. Arthur D. Friedman, Melvin A. Breuer and Miron Abramovci, "Digital Systems Testing And Testable Design", A Jaico Book, 2006.
  16. X. Du, N. Mukherjee, W.T Cheng and S.M Reddy, "Full- speed field-programmable memory BIST architecture", Proc. of mt. Test Conference, pp. 1173-1182, 2005
  17. X. Du, N. Mukheijee, W-T Cheng, S. M. Reddy, "A Field-Programmable Memory BIST Architecture Supporting Algorithms and Multiple Nested Loops", Proc. of the Asian Test Symposium, paper 45.3, 2006.

IInternational Journal of Scientific Research in Computer Science, Engineering and Information Technology

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Published

2017-08-31

Issue

Volume 2, Issue 4, July-August-2017

Section

Research Articles

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How to Cite

[1]
V. Rajendra Chary , " Design of Alu-Based Symmetric Transparent Online BIST for RAM , IInternational Journal of Scientific Research in Computer Science, Engineering and Information Technology(IJSRCSEIT), ISSN : 2456-3307, Volume 2, Issue 4, pp.729-732, July-August-2017.