Design of Alu-Based Symmetric Transparent Online BIST for RAM

Authors(1) :-V. Rajendra Chary

A 3-bit RAM is tested using 5-bit ALU with the help of symmetric transparent online BIST scheme. This architecture skips signature prediction. It also reduces test time. If the RAM output consists if all 1’s, then it indicates that there is no error in the RAM module, otherwise it indicates that there is an error. The implemented scheme utilizes an ALU in order to generate the test pattern and compress the responses of the memory module, the word width of memory can be smaller than the number of stages of ALU. Hence multiple non-identical memories can also be tested in a pipeline way. All synthesis and simulation results are performed using xilinx14.2 ISE

Authors and Affiliations

V. Rajendra Chary
Department of Electronics and Communication Engineering, Sreenidhi Institute of Science and Technology, Affiliated to Jawaharlal Nehru Technological University, Hyderabad, Telangana, India

RAM, Signature Prediction, Test Pattern

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Publication Details

Published in : Volume 2 | Issue 4 | July-August 2017
Date of Publication : 2017-08-31
License:  This work is licensed under a Creative Commons Attribution 4.0 International License.
Page(s) : 729-732
Manuscript Number : CSEIT1172494
Publisher : Technoscience Academy

ISSN : 2456-3307

Cite This Article :

V. Rajendra Chary , "Design of Alu-Based Symmetric Transparent Online BIST for RAM ", International Journal of Scientific Research in Computer Science, Engineering and Information Technology (IJSRCSEIT), ISSN : 2456-3307, Volume 2, Issue 4, pp.729-732, July-August-2017.
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