Design of High-Speed Low Power Full Adder Using TFET

Authors(2) :-R. Gowtham Raj, V. Bakya Lakshmi

A full adder circuit is considered as one of the fundamental building block for Digital Signal Processors (DSPs), Arithmetic and Logical Units (ALUs), Application Specific Integrated Circuits (ASICs) in VLSI design. So speed power and area are the three main design metrics for any VLSI circuits. The speed of the higher level design depends on the speed of full adder circuits. Thus realizing an efficient adder is required for better performance of an ALU and therefore the processor. A low power and high performance 1-bit full adder is proposed. In the existing system 8T NMOS full adder technique has been used. This NMOS full adder provides low speed and consumes more power. The major disadvantage is load capacitance effect. Compared to earlier designed NMOS full adder, the proposed TFET full adder shows a significant improvement in Power Delay Product (PDP), and speed. The simulation and power analysis are carried out using cadence virtuoso environment with 180 nm technology.

Authors and Affiliations

R. Gowtham Raj
Computer Science and Engineering, Anna University/IFET College of Engineering, Villupuram, Tamil Nadu, India
V. Bakya Lakshmi
Computer Science and Engineering, Anna University/IFET College of Engineering, Villupuram, Tamil Nadu, India

Tunnel FET; Full adder; PTL(Pass Transistor Logic;, Speed; Power; ALU(Arithmetic and Logical Unit);Transistor(T);

  1. Debanjana Datta and Debarshi Datta, “A novel power efficient N-MOS based 1-bit full adder”, Microelectronics, Computing and Communications (MicroCom), 2016 International Conference.
  2. Kumar, S. K. Arya, S. Pandey, “Single bit full adder design using 8 transistors with novel 3 transistors XNOR gate” International Journal of VLSI design & Communication Systems (VLSICS) December 2011.
  3. Reddy, and G. Karthik, "Low power area designs of 1-bit full adder in cadence virtuoso platform" International Journal of VLSI Design & Communication Systems, 2013.
  4. Shekhar Verma, “New High Performance 1-Bit Full Adder Using Domino Logic”, 2014
  5. DivyaBharathi, and B.N. S. Rao, “Design and Implementation of Low-Power High- Speed Full Adder cell using GDI Technique”, IJESIT, March 2013.
  6. Satish M Turkane, “Review of Tunnel Field Effect Transistor (TFET)” International Journal of Applied Engineering Research, 2016.
  7. Ravindhiran Mukundrajan, Matthew Cotter “Ultra Low Power Circuit Design using Tunnel FETs”, IEEE Computer Society Annual Symposium on VLSI, 2012.

Publication Details

Published in : Volume 2 | Issue 2 | March-April 2017
Date of Publication : 2017-04-30
License:  This work is licensed under a Creative Commons Attribution 4.0 International License.
Page(s) : 681-685
Manuscript Number : CSEIT1722216
Publisher : Technoscience Academy

ISSN : 2456-3307

Cite This Article :

R. Gowtham Raj, V. Bakya Lakshmi, "Design of High-Speed Low Power Full Adder Using TFET", International Journal of Scientific Research in Computer Science, Engineering and Information Technology (IJSRCSEIT), ISSN : 2456-3307, Volume 2, Issue 2, pp.681-685, March-April-2017.
Journal URL :

Article Preview