Design of High-Speed Low Power Full Adder Using TFET

Abstract

A full adder circuit is considered as one of the fundamental building block for Digital Signal Processors (DSPs), Arithmetic and Logical Units (ALUs), Application Specific Integrated Circuits (ASICs) in VLSI design. So speed power and area are the three main design metrics for any VLSI circuits. The speed of the higher level design depends on the speed of full adder circuits. Thus realizing an efficient adder is required for better performance of an ALU and therefore the processor. A low power and high performance 1-bit full adder is proposed. In the existing system 8T NMOS full adder technique has been used. This NMOS full adder provides low speed and consumes more power. The major disadvantage is load capacitance effect. Compared to earlier designed NMOS full adder, the proposed TFET full adder shows a significant improvement in Power Delay Product (PDP), and speed. The simulation and power analysis are carried out using cadence virtuoso environment with 180 nm technology.