Design and Implementation of Basic Logic Gates and Adder Circuits with Memristor

Authors(2) :-S. Govardhana Rao, Y. Bhavani Prasad

The "memristor" was actually deducted by Leon Chua, a mathematician in 1971, with no actual realization or physical presentation of it. This research focuses on implementing the component into hybrid electronic device that would give identical result to its identical device which is fully CMOS structured. The research includes integrating spice-model of the memristor into appropriate software for simulation, in this paper; I have designed a hybrid Memristor-CMOS (MeMOS) logic based adder circuit that can be used in based logic computational architectures. I have also analyzed the transient response of logic gates designed using MeMOS logic circuits. MeMOS use CMOS 180 nm process with memristor to compute Boolean logic operations. Various parameters including Ares, delay and power dissipation are computed and compared with standard CMOS 180 nm logic design. The proposed logic shows better area utilization and excellent results from existing CMOS logic circuits at standard 1.8 V operating voltage.

Authors and Affiliations

S. Govardhana Rao
Department of ECE, Gudlavalleru Engineering College, Gudlavalleru, Andhra Pradesh, India
Y. Bhavani Prasad
Department of ECE, Gudlavalleru Engineering College, Gudlavalleru, Andhra Pradesh, India

Memristor, Memristor-CMOS (MeMOS) Logic, full adder, logic gates

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Publication Details

Published in : Volume 2 | Issue 3 | May-June 2017
Date of Publication : 2017-06-30
License:  This work is licensed under a Creative Commons Attribution 4.0 International License.
Page(s) : 646-654
Manuscript Number : CSEIT1723216
Publisher : Technoscience Academy

ISSN : 2456-3307

Cite This Article :

S. Govardhana Rao, Y. Bhavani Prasad, "Design and Implementation of Basic Logic Gates and Adder Circuits with Memristor", International Journal of Scientific Research in Computer Science, Engineering and Information Technology (IJSRCSEIT), ISSN : 2456-3307, Volume 2, Issue 3, pp.646-654, May-June-2017.
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