Design and Implementation of Modified Vedic Multiplier in FPGA Design Using Zero Knowledge Verification Key

Authors(2) :-D. Indhu, Prof. S. Kamatchi

Watermarking as a novel intellectual property protection technique, here the 16Bit Vedic Multiplier is used and it is designed by using AHL circuit and Razor Flip-flop for reducing delay of operation. This modified Vedic multiplier is implemented in FPGA (Xilinx Vertex – 5 Board). With the use of Zero knowledge verification protocol, the FPGA’s Intellectual Property are protect from infringement. This project proposes a new watermarking detection technique based on chaos-based zero-knowledge interaction with Digital signature. The digital signature is watermarked and it is used as a verification key. This digital signature is retrieved by zero knowledge verification protocol. The zero knowledge algorithms is a cryptography based network security algorithm. This protocol is used to resist the sensitive information leakage and embedding attack and is thus robust to the cheating from the prover, verifier, or third party. The result may get better robustness than the most recent related literature.

Authors and Affiliations

D. Indhu
PG Student, Akshaya College of Engineering and Technology, Coimbatore, Tamil Nadu, India
Prof. S. Kamatchi
Assistant professor, Akshaya College of Engineering and Technology, Coimbatore, Tamil Nadu, India

Vedic Multiplier; Watermarking; Zero Knowledge Algorithm; FPGA,AHL, Razor Flipflop;

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Publication Details

Published in : Volume 2 | Issue 5 | September-October 2017
Date of Publication : 2017-10-31
License:  This work is licensed under a Creative Commons Attribution 4.0 International License.
Page(s) : 831-836
Manuscript Number : CSEIT1725192
Publisher : Technoscience Academy

ISSN : 2456-3307

Cite This Article :

D. Indhu, Prof. S. Kamatchi, "Design and Implementation of Modified Vedic Multiplier in FPGA Design Using Zero Knowledge Verification Key", International Journal of Scientific Research in Computer Science, Engineering and Information Technology (IJSRCSEIT), ISSN : 2456-3307, Volume 2, Issue 5, pp.831-836, September-October-2017.
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