Design and Implementation of Modified Vedic Multiplier in FPGA Design Using Zero Knowledge Verification Key

Authors(2) :-D. Indhu, Prof. S. Kamatchi

Watermarking as a novel intellectual property protection technique, here the 16Bit Vedic Multiplier is used and it is designed by using AHL circuit and Razor Flip-flop for reducing delay of operation. This modified Vedic multiplier is implemented in FPGA (Xilinx Vertex – 5 Board). With the use of Zero knowledge verification protocol, the FPGA’s Intellectual Property are protect from infringement. This project proposes a new watermarking detection technique based on chaos-based zero-knowledge interaction with Digital signature. The digital signature is watermarked and it is used as a verification key. This digital signature is retrieved by zero knowledge verification protocol. The zero knowledge algorithms is a cryptography based network security algorithm. This protocol is used to resist the sensitive information leakage and embedding attack and is thus robust to the cheating from the prover, verifier, or third party. The result may get better robustness than the most recent related literature.

Authors and Affiliations

D. Indhu
PG Student, Akshaya College of Engineering and Technology, Coimbatore, Tamil Nadu, India
Prof. S. Kamatchi
Assistant professor, Akshaya College of Engineering and Technology, Coimbatore, Tamil Nadu, India

Vedic Multiplier; Watermarking; Zero Knowledge Algorithm; FPGA,AHL, Razor Flipflop;

  1. Jiliang Zhang and Lele Liu, “ Publicly Verifiable Watermarking for Intellectual Property Protection in FPGA Design” Vol 25 | Issue 4, April 2017 IEEE (pp.1520-1527).
  2. J. Zhang, Y. Lin, Q. Wu, and W. Che, “Watermarking FPGA bit file for intellectual property protection”, Radio engineering, vol. 21, no. 2,pp. 764-771, Jun. 2012.
  3. Saha, P., Banerjee, A., Bhattacharyya, P., and Dandapat, A. ”High speed ASIC design of complex multiplier using vedic mathematics”. In Students Technology Symposium, Jan. 2011 IEEE (pp. 237-241).
  4. Anuva Das, Mrs.J.K.Kasthuri Bhai, “Design Optimization of Vedic Multiplier using Reversible Logic” International Journal of Engineering Research & Technology (IJERT), Vol. 3 Issue 3, March 2014, ISSN: 2278-0181.
  5. Vaijyanath Kunchigi, Linganagouda Kulkarni, SubhashKulkarni, “High Speed and Area Efficient Vedic Multiplier”, IEEE, Devices, Circuits and systems,Vol.4,pp.360-364,15-16 March 2012.
  6. Sudeep.M.C, SharathBimba.M, “Design and FPGA Implementation of High Speed Vedic Multiplier”, International Journal of Computer Applications, Vol. 90, Issue 16, March 2014.
  7. M.A. Gora, A. Maiti and Schaumont, “A Flexible design flow for software IP binding in FPGA,” IEEE Trans. Ind Informat, vol.6, no. 4, pp.719-728, Nov. 2010.
  8. D.Saha and S.Sur-Kolay, “ Secure public verification of IP marks in FPGA design through a zero knowledge protocol,” IEEE Trans. Very Large Scale Integr. (VLSI) Syst, vol. 20, no.10, pp. 1749-1757. Oct. 2012.
  9. Gupta.A, Malviya.U, Kapse. V, “A Novel Approach To Design A High Speed Arithmetic Logic Unit Based on Ancient Vedic Multiplier Technique”, International Journal of Modern Engineering Research (IJMER), Vol. 2, Issue4, pp. 2695-2698, July-Aug 2012.
  10. Ramachandran S, Pande K.S, “Design, Implementation and Performance Analysis of an Integrated Vedic Multiplier Architecture”, International Journal of Computational Engineering Research, Vol.2 Issue3, pp. 697-703, May-June 2012.
  11. J.Kufel, P.R Wilson, S. Hill, B.M.AI-Hashimi, and P.N.Whatmough, “Sequence-aware watermark design for soft IP embedded processors”, IEEE Trans. Very Large Scale Integr. (VLSI) Syst, vol. 24, no.1, pp. 276-289, Jan. 2016.
  12. S.Trimberger, J.Moore and W.Lu, “Authenticated encryption for FPGA bitstreams”, in proc. ACM/SIGDA Int. sysp. Field Program. Gate Arrays, 2011,pp.83-86.

Publication Details

Published in : Volume 2 | Issue 5 | September-October 2017
Date of Publication : 2017-10-31
License:  This work is licensed under a Creative Commons Attribution 4.0 International License.
Page(s) : 831-836
Manuscript Number : CSEIT1725192
Publisher : Technoscience Academy

ISSN : 2456-3307

Cite This Article :

D. Indhu, Prof. S. Kamatchi, "Design and Implementation of Modified Vedic Multiplier in FPGA Design Using Zero Knowledge Verification Key", International Journal of Scientific Research in Computer Science, Engineering and Information Technology (IJSRCSEIT), ISSN : 2456-3307, Volume 2, Issue 5, pp.831-836, September-October-2017.
Journal URL : http://ijsrcseit.com/CSEIT1725192

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