Orthogonal Latin Squares Encoders and Syndrome Computation with Concurrent Error Detection

Authors(1) :-P. Divya

Error Correction Codes (ECCS) Are Commonly Used To Protect Memories Against Errors. Among Eccs, Orthogonal Latin Squares (OLS) Codes Have Gained Renewed Interest For Memory Protection Due Tot heir Modularity And The Simplicity Of The Decoding Algorithm That Enables Low Delay Implementations. An Important Issue Is That When ECCS Are Used, The Encoder And Decoder Circuits Can Also Suffer Errors. In This Brief, A Concurrent Error Detection Technique For OLS Codes Encoders And Syndrome Computation Is Proposed And Evaluated. The Proposed Method Uses The Properties Of OLS Codes To Efficiently Implement A Parity Prediction Scheme That Detects All Errors That Affect A Single Circuit Node.

Authors and Affiliations

P. Divya
Department of Electronics and Communication Engineering, Medha College of Engineering, Affiliated to Jawaharlal Nehru Technological University, Hyderabad, Telangana, India

Concurrent Error Detection, Error Correction Codes (ECC), Latin Squares, Majority Logic Decoding (MLD), Memory, OLS Codes.

  1. C. L. Chen and M. Y. Hsiao, "Error-correcting codes for semiconductor memory applications: A state-of-the-art review," IBM J. Res. Develop., vol. 28, no. 2, pp. 124-134, Mar. 1984.
  2. E. Fujiwara, Code Design For Dependable Systems: Theory And Practicalapplication. New York: Wiley, 2006.
  3. A. Dutta And N. A. Touba, "Multiple Bit Upset Tolerant Memory Using Aselective Cycle Avoidance Based Sec-Ded-Daec Code," In Proc. Ieeevlsi Test Symp., May 2007, Pp. 349-354.
  4. R. Naseer And J. Draper, "Dec Ecc Design To Improve Memory Reliabilityin Sub-100nm Technologies," In Proc. Ieee Int. Conf. Electron.,Circuits, Syst., Sep. 2008, Pp. 586-589.
  5. G. C. Cardarilli, M. Ottavi, S. Pontarelli, M. Re, And A. Salsano, "Faulttolerant Solid State Mass Memory For Space Applications," Ieee Trans.Aerosp. Electron. Syst., Vol. 41, No. 4, Pp. 1353-1372, Oct. 2005.
  6. S. Lin And D. J. Costello, Error Control Coding, 2nd Ed. Englewoodcliffs, Nj: Prentice-Hall, 2004.
  7. S. Ghosh And P. D. Lincoln, "Dynamic Low-Density Parity Check Codesfor Fault-Tolerant Nano-Scale Memory," In Proc. Found. Nanosci., 2007,Pp. 1-5.
  8. H. Naeimi And A. Dehon, "Fault Secure Encoder And Decoder Fornanomemory Applications," Ieee Trans. Very Large Scale Integr. (Vlsi)Syst., Vol. 17, No. 4, Pp. 473-486, Apr. 2009.
  9. S. Liu, P. Reviriego, And J. A. Maestro, "Efficient Majority Logicfault Detection With Difference-Set Codes For Memory Applications,"Ieee Trans. Very Large Scale Integr. (Vlsi) Syst., Vol. 20, No. 1,Pp. 148-156, Jan. 2012.
  10. M. Y. Hsiao, D. C. Bossen, And R. T. Chien, "Orthogonal Latinsquare Codes," Ibm J. Res. Develop., Vol. 14, No. 4, Pp. 390-394,Jul. 1970.
  11. S. E. Lee, Y. S. Yang, G. S. Choi, W. Wu, And R. Iyer, "Low-Power,Resilient Interconnection With Orthogonal Latin Squares," Ieee Designtest Comput., Vol. 28, No. 2, Pp. 30-39, Mar.-Apr. 2011.
  12. R. Datta And N. A. Touba, "Generating Burst-Error Correcting Codes Fromorthogonal Latin Square Codes-A Graph Theoretic Approach," In Proc. Ieeeint. Symp. Defect Fault Tolerance Vlsi Nanotechnol. Syst., Oct. 2011, Pp. 367-373.
  13. A. R. Alameldeen, Z. Chishti, C. Wilkerson, W. Wu, And S.-L. Lu,"Adaptive Cache Design To Enable Reliable Low-Voltage Operation," Ieee Trans. Comput., Vol. 60, No. 1, Pp. 50-63, Jan. 2011.
  14. G. C. Cardarilli, S. Pontarelli, M. Re, And A. Salsano, "Concurrent Error Detection In Reed-Solomon Encoders And Decoders," Ieee Trans.Very Large Scale Integr. (Vlsi) Syst., Vol. 15, No. 7, Pp. 842-846,Jul. 2007.
  15. I. M. Boyarinov, "Self-Checking Circuits And Decoding Algorithmsfor Binary Hamming And Bch Codes And Reed-Solomon Codes Overgf(2m)," Prob. Inf. Transmiss., Vol. 44, No. 2, Pp. 99-111, 2008.
  16. H. Jaber, F. Monteiro, S. J. Piestrak, And A. Dandache, "Designof Parallel Fault-Secure Encoders For Systematic Cyclic Block Transmissioncodes," Microelectron. J., Vol. 40, No. 12, Pp. 1686-1697,Dec. 2009.
  17. S. J. Piestrak, A. Dandache, And F. Monteiro, "Designing Fault-Secureparallel Encoders For Systematic Linear Error Correcting Codes," Ieee Trans. Reliab., Vol. 52, No. 4, Pp. 492-500, Apr. 2003.
  18. J. A. Maestro, P. Reviriego, C. Argyrides, And D. K. Pradhan, "Faulttolerant Single Error Correction Encoders," J. Electron. Test., Theoryappl., Vol. 27, No. 2, Pp. 215-218, Apr. 2011.
  19. J. Denes And A. D. Keedwell, Latin Squares And Their Applications.San Francisco, Ca: Academic, 1974.
  20. P. K. Lala, Self-Checking And Fault-Tolerant Digital Design. Sanmateo,Ca: Morgan Kaufmann, 2001.

Publication Details

Published in : Volume 2 | Issue 6 | November-December 2017
Date of Publication : 2017-12-31
License:  This work is licensed under a Creative Commons Attribution 4.0 International License.
Page(s) : 568-572
Manuscript Number : CSEIT1726168
Publisher : Technoscience Academy

ISSN : 2456-3307

Cite This Article :

P. Divya, "Orthogonal Latin Squares Encoders and Syndrome Computation with Concurrent Error Detection", International Journal of Scientific Research in Computer Science, Engineering and Information Technology (IJSRCSEIT), ISSN : 2456-3307, Volume 2, Issue 6, pp.568-572, November-December-2017.
Journal URL : http://ijsrcseit.com/CSEIT1726168

Article Preview