Realization of Redundant Binary Multiplier with Modified Partial Product Generator Using Verilog

Authors(3) :-V. Lakshma Reddy, H. Sudhakar, D. Ajay Kumar

Digital multipliers are widely used in arithmetic units of microprocessors, multimedia and digital signal processors. A redundant binary (RB) representation can be used when designing high performance multipliers due to its high modularity and carry-free addition. The conventional RB multiplier requires an additional RB partial product (RBPP) row, because an error-correcting word (ECW) is generated by both the radix-4 Modified Booth encoding (MBE) and the RB encoding. This incurs in an additional RBPP accumulation stage for the MBE multiplier. In this paper, a new RB modified partial product generator (RBMPPG) is proposed; it removes the extra ECW and hence, it saves one RBPP accumulation stage. Therefore, the proposed RBMPPG generates fewer partial product rows than a conventional RB MBE multiplier. Simulation results show that the proposed RBMPPG based designs significantly improve the area and power consumption when the word length of each operand in the multiplier is at least 32 bits.

Authors and Affiliations

V. Lakshma Reddy
M.Tech (VLSI Design), Department of ECE, SIR C.R.R. College of Engineering, Eluru,Andhra Pradesh, India
H. Sudhakar
Assistant Professor, Department of ECE, SIR C.R.R. College of Engineering, Eluru, Andhra Pradesh, India
D. Ajay Kumar
Assistant Professor, Department of ECE, SIR C.R.R. College of Engineering, Eluru, Andhra Pradesh, India

Binary Multiplier, Verilog, Partial Product Generator, ECW, RBMPPG, MBE, RBPP, RB MBE Multiplier, Normal Binary, MBE

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Publication Details

Published in : Volume 2 | Issue 6 | November-December 2017
Date of Publication : 2017-12-31
License:  This work is licensed under a Creative Commons Attribution 4.0 International License.
Page(s) : 924-929
Manuscript Number : CSEIT1726264
Publisher : Technoscience Academy

ISSN : 2456-3307

Cite This Article :

V. Lakshma Reddy, H. Sudhakar, D. Ajay Kumar, "Realization of Redundant Binary Multiplier with Modified Partial Product Generator Using Verilog", International Journal of Scientific Research in Computer Science, Engineering and Information Technology (IJSRCSEIT), ISSN : 2456-3307, Volume 2, Issue 6, pp.924-929, November-December-2017.
Journal URL : http://ijsrcseit.com/CSEIT1726264

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