Optimization of Worst-Case Execution Time for ASIP using Genetic Algorithm

Authors(3) :-Mood Venkanna, Rameshwar Rao, P. Chandra Sekhar

The use of Application Specific Processor is available almost in all the areas. Research and developments on ASIP has been progressed since last two decades. However, the minute analysis of these processors is still a great challenge for the engineers and researchers in current scenario. Embedded processor application spread over different areas with a high desire of fast and accurate execution. It requires enhancing the execution time of the processor. The worst-case execution time (WCET) evaluation satisfies the desire of user end along with the hardware and software application of the processor. As a result the reconfiguration of processor architecture can be modified and perfect task scheduling can be performed. For WCET, upper bound on execution time is to be focused. An attempt is made to optimize the WCET to enhance the performance of the processor along with less occupation of space. Genetic Algorithm (GA) as the popular optimization technique is utilized to optimize that can help to the reconfigurable processor performance and also the control flow of the instruction to the processors.

Authors and Affiliations

Mood Venkanna
Department of ECE, UCE, Osmania University, Hyderabad, India
Rameshwar Rao
Former VC JNTUH, Department of ECE, UCE, Osmania University, Hyderabad, India
P. Chandra Sekhar
Professor, Department of ECE, UCE, Osmania University, Hyderabad, India

Embedded processor, ASIP, Optimization, Genetic Algorithm, WCET.

  1. Asavoae, M., Maiza,C. Raymond, P., 2013, Program Semantics in Model-Based WCET Analysis: A State of the Art Perspective. WCET Ed. by Claire Maiza. OASICS. 30, 32–41.
  2. ClementBallabriga et al., 2010, OTAWA: An Open Toolbox for Adaptive WCET Analysis. SEUS. LNCS. Springer, 6399, 35–46.
  3. Banerjee,A., Chattopadhyay,S. and Roychoudhury,A., 2013, Precise micro architectural modeling for WCET analysis via AI+SAT. IEEE Real-Time and Embedded Technology and Applications Sym- posium (RTAS), IEEE Computer Society, 87–96.
  4. Armin Biere et al., 2013, The Auspicious Couple: Symbolic Execution and WCET Analysis. WCET, OASIcs. IBFI Schloss Dagstuhl, 30. 53–63. http://drops.dagstuhl.de/opus/volltexte/2013/4122.
  5. Bjorner,N. Dutertre,B. and Moura, L., 2008, Accelerating lemma learning using joins - DPLL(?). Appeared as short paper in LPAR 2008, outside of proceedings.
  6. Cadar, C. and Sen, K.., 2013, Symbolic Execution for Software Testing: Three Decades Later. Commun. ACM 56.2, 82–90.
  7. Caspi,P., Raymond P., and Tripakis, S., 2008, Synchronous Programming. Handbook of Real- Time and Embedded Systems. Chapman & Hall / CRC, Chap. 14.
  8. Chaki, S., and Ivers, J., 2010, Software model checking without source code. English. Innovations in Systems and Software Engineering 6.3, 233–242. ISSN: 1614-5046. doi: 10.1007/s11334-010- 0125-0.
  9. Chattopadhyay, S., and Roychoudhury, A., 2013 Scalable and precise refinement of cache timing analysis via path-sensitive verification. Real-Time Systems 49.4, 517–562.
  10. Chu, D., and Jaffar, J., 2011, Symbolic simulation on complicated loops for WCET Path Analysis.EMSOFT. 319–328. ISBN: 978-1-4503-0714-7. doi: 10.1145/2038642.2038692.
  11. Wilhelm, R., 2006, Determining Bounds on Execution Times. Handbook on Embedded Systems. CRC Press, Chap. 14.
  12. Reinhard Wilhelm et al., 2008, The worst-case execution-time problem - overview of methods and survey of tools. ACM Trans. Embedded Comput. Syst.7.3.
  13. Wankang Zhao et al., 2006, Improving WCET by applying worst-case path optimizations. Real- Time Systems 34.2, 129–152.
  14. Kim,S.K., Min, S. L. and Ha,R., 1996, Efficient Worst Case Timing Analysis of Data Caching.IEEE Real-Time Technology and Applications Symposium (RTAS’96). 230–240.
  15. White,R., Muller, F. , Healy,C., Whalley,D., and Harmon, M.,1997, Timing Analysis for Data Caches and Set-Associative Caches. IEEE Real-Time Technology and Applications Symposium (RTAS’97), 192–202.
  16. Colin, A. and Puaut, I., 2000, Worst Case Execution Time Analysis for a Processor with Branch Prediction.Journal of Real-Time Systems, 18, 2/3, 249–274.
  17. Mitra, T. and Roychoudhury, A. , 2001, Effects of Branch Prediction on Worst Case Execution Time of Programs. National University of Singapore (NUS),Tech. Rep. 11-01.

Publication Details

Published in : Volume 2 | Issue 7 | September 2017
Date of Publication : 2017-09-30
License:  This work is licensed under a Creative Commons Attribution 4.0 International License.
Page(s) : 316-322
Manuscript Number : CSEIT174438
Publisher : Technoscience Academy

ISSN : 2456-3307

Cite This Article :

Mood Venkanna, Rameshwar Rao, P. Chandra Sekhar, "Optimization of Worst-Case Execution Time for ASIP using Genetic Algorithm", International Journal of Scientific Research in Computer Science, Engineering and Information Technology (IJSRCSEIT), ISSN : 2456-3307, Volume 2, Issue 7, pp.316-322, September-2017.
Journal URL : http://ijsrcseit.com/CSEIT174438

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