Multi Bit Errors Prediction and Correction in Memories Using Cost Efficient 64-Bit DMC

Authors(2) :-M Sarath Kumar, H Chandrasekhar

This paper presents a cost efficient technique to correct Multiple Bit Upsets (MBUs) to protect memories against radiation. To protect memories from MBUs, many complex error correction codes (ECCs) were used previously, but the major issue is higher redundant memory overhead. In this paper 64-bit Matrix Code was proposed to assure the reliability of memory. The proposed protection code utilized procedure to detect errors, so that more errors were detected and corrected. The results showed that the proposed scheme has a protection level against large MBUs in memory. Transient multiple bit upsets (MBUs) are suitable major problems in the reliability of memories exposed to radiation environment. In the proposed method we are implement 32-bit matrix for error correction in memories. To prevent MBUs from causing data corruption, more complex error correction codes (ECCs) are widely used to protect memory, but the main problem is that they would require higher delay overhead. Recently, matrix codes (MCs) based on Hamming codes include been proposed for memory protection. The main issue is that they are double error correction codes and the error correction capabilities are not enhanced in all cases. Moreover, the erasure codes is proposed to reduce the area overhead of extra circuits exclusive of disturbing the total encoding and decoding processes. Now a days to maintain good level of reliability, it is necessary to protect memory bits using protection codes, for this purpose, various error detection and correction methods are being used. The only drawback of the existing MC is that more redundant bits are required to maintain higher reliability of memory. The proposed technique used matrix code to assure reliability in presence of multiple bit upset and reduce more redundant bit and its correct more error compare to existing system.

Authors and Affiliations

M Sarath Kumar
MTech Scholar, Department of ECE, Vemu Institute of Technology, Chittoor, Andhra Pradesh , India
H Chandrasekhar
Associate Professor, Department of ECE, Vemu Institute of Technology, Chittoor, Andhra Pradesh, India

FPGA, Multiple Bit Upsets, Reliability, Soft Errors

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Publication Details

Published in : Volume 3 | Issue 1 | January-February 2018
Date of Publication : 2018-02-28
License:  This work is licensed under a Creative Commons Attribution 4.0 International License.
Page(s) : 181-188
Manuscript Number : CSEIT183120
Publisher : Technoscience Academy

ISSN : 2456-3307

Cite This Article :

M Sarath Kumar, H Chandrasekhar, "Multi Bit Errors Prediction and Correction in Memories Using Cost Efficient 64-Bit DMC", International Journal of Scientific Research in Computer Science, Engineering and Information Technology (IJSRCSEIT), ISSN : 2456-3307, Volume 3, Issue 1, pp.181-188, January-February.2018
URL : http://ijsrcseit.com/CSEIT183120

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