Design and Verilog HDL Implementation of Carry Skip Adder Using Kogge-Stone Tree Logic

Authors(2) :-K. Reshma Priyanka, A. M. Gunasekhar

The portable equipment’s such as cellular phones, Personal Digital Assistant (PDA), and notebook personal computer, arise the need of effective circuit area and power efficient VLSI circuits. Addition is the most common and often used arithmetic operation in digital computers and also, it serves as a building block for synthesis all other arithmetic operations. In this paper, we present a carry skip adder (CSKA) structure that has a higher speed yet lower energy consumption compared with the conventional one. The speed enhancement is achieved by applying concatenation and incrementation schemes to improve the efficiency of the conventional CSKA (ConvCSKA) structure. In addition, instead of utilizing multiplexer logic, the proposed structure makes use of AND-OR-Invert (AOI) and OR-AND-Invert (OAI) compound gates for the skip logic. The structure may be realized with both fixed stage size and variable stage size styles, wherein the latter further improves the speed and energy parameters of the adder. The proposed method uses compound gates such as AOI and OAI as skip logic in the design that leads to decrease area usage, delay and power consumption, also in addition the parallel prefix kogge stone adder is included to attain further reduction of power. The design is coded in Verilog HDL and its simulation, area, delay and power are analyzed using Xilinx_ISE 14.3.

Authors and Affiliations

K. Reshma Priyanka
M.Tech Student, Department of ECE, Sree Rama Institute of Technical Education, Tirupathi, India
A. M. Gunasekhar
HOD & Associate Professor, Department of ECE, Sree Rama Institute of Technical Education, Tirupathi, India

Carry skip adder, AND-OR-Invert logic, KoggeStone adder, hybrid variable latency adders.

  1. Alito and G. Palumbo, "A simple strategy for optimized design of one-level carry-skip adders," IEEE Trans. Circuits Syst. I, Fundam. Theory. Appl., Vol. 50, no. 1, pp. 141-148, Jan. 2003.
  2. Chen, H. Li, J. Li and C. K. Koh, "Variable-latency adder (VL-adder): New arithmetic circuit design practice to overcome NBTI", in Proc. ACM/IEEE Int. Symp. Low Power Electron. Design (ISLPED), Aug. 2007, pp. 195-200.
  3. Chirca et al., "A static low-power, high-performance 32-bit carry skip adder", in Proc. Euromicro Symp. Digit. Syst. Design (DSD), Aug./Sep. 2004, pp. 615- 619.
  4. Du, P. Varman and K. Mohanram, "High performance reliable variable latency carry select addition", in Proc. Design Autom., Test Eur. Conf. Exhibit. (DATE), Mar. 2012, pp. 1257-1262.
  5. Ghosh and K. Roy, "Exploring high-speed lowpower hybrid arithmetic units at scaled supply and adaptive clock-stretching", in Proc. Asia South Pacific Design Autom. Conf. (ASPDAC), Mar.2008, pp. 635-640.
  6. Jia et al., "static CMOS implementation of logarithmic skip adder", in Proc. IEEE Conf. Electron Devices Solid-State Circuits, Dec. 2003, pp. 509-512.
  7. Kantabutra, "Designing optimum one-level carryskip adders", IEEE Trans. Comput., Vol. 42, no. 6, pp. 759-764, Nov. 1993.
  8. Milad Bahadori, Mehdi Kamal and Ali AfzaliKusha,"„High-speed and energy efficient carry skip adder operating under a wide range of supply voltage levels", IEEE Transaction on Very Large Scale Integration (VLSI) Systems, 2015, Vol. 67, no. 4, pp. 324-335.
  9. G. Oklobdzija, B. R. Zeydel, H. Dao ,S. Mathew, and R. Krishnamurthy, "Energy-delay estimation technique for high-performance microprocessor VLSI adders", in proc. 16th IEEE Symp. Comput. Arithmetic, Jun. 2003, pp.272-279.
  10. Kaveri, P.Senthil Kumar, "An Efficient Architecture of Carry Select Adder using Logic Formulation", International Journal of Science and Research(IJSR), Vol 5, no.2, pp. 1444-1447, Feb 2016.
  11. Ramkumar and H. M. Kittur, "Low-power and areaefficient carry select adders", IEEE Trans. Very Large Scale Integr. (VLSI) Syst., Vol. 20, no. 2, pp. 371-375, Feb. 2012.
  12. R. Zlatanovici, S. Kao, and B. Nikolic, "Energy-delay optimization of 64-bit carry-lookahead adders with a 240 ps 90 nm CMOS design example", IEEE J. SolidState Circuits, Vol. 44, no. 2, pp. 569-583, Feb. 2009.

Publication Details

Published in : Volume 3 | Issue 1 | January-February 2018
Date of Publication : 2018-02-28
License:  This work is licensed under a Creative Commons Attribution 4.0 International License.
Page(s) : 904-911
Manuscript Number : CSEIT1831226
Publisher : Technoscience Academy

ISSN : 2456-3307

Cite This Article :

K. Reshma Priyanka, A. M. Gunasekhar, "Design and Verilog HDL Implementation of Carry Skip Adder Using Kogge-Stone Tree Logic", International Journal of Scientific Research in Computer Science, Engineering and Information Technology (IJSRCSEIT), ISSN : 2456-3307, Volume 3, Issue 1, pp.904-911, January-February-2018.
Journal URL :

Article Preview