High-Speed and Low Delay Parallel Prefix Adder with Skip Logic

Authors(2) :-Botla Mounika, K. Sundeep

A carry skip adder (CSKA) structure is presented which has lower power consumption with a higher speed. The performance of the conventional CSKA is improved by achieving the speed enhancement by applying concatenation and incrementation schemes. The existed structure utilizes AND-OR-INVERT (AOI) and OR-AND-INVERT (OAI) compound gates for the skip logic. Low power very large scale integration (VLSI) circuits are most significant for designing of high performance and portable devices. The high speed, small area and low cost are the main considerations of VLSI circuits. This paper presents the design and hardware implementation of Hybrid variable latency CSKA. The proposed design is simulated using ISE simulator. The design shows 38% improvement in speed and 11.53% improvement in area compared to carry look ahead adder. The maximum power consumption for proposed system is 0.014W.

Authors and Affiliations

Botla Mounika
M. Tech-Scholar, Department of ECE, Pace Institute of Technology and Sciences, Ongole, Andhra Pradesh, India
K. Sundeep
Associate Professor, Department of ECE, Pace Institute of Technology and Sciences, Ongole, Andhra Pradesh, India

Serial Adder, Parallel Prefix Adder, Kogge Stone Adder, High speed VLSI.

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Publication Details

Published in : Volume 3 | Issue 1 | January-February 2018
Date of Publication : 2018-02-28
License:  This work is licensed under a Creative Commons Attribution 4.0 International License.
Page(s) : 1110-1113
Manuscript Number : CSEIT1831301
Publisher : Technoscience Academy

ISSN : 2456-3307

Cite This Article :

Botla Mounika, K. Sundeep, "High-Speed and Low Delay Parallel Prefix Adder with Skip Logic", International Journal of Scientific Research in Computer Science, Engineering and Information Technology (IJSRCSEIT), ISSN : 2456-3307, Volume 3, Issue 1, pp.1110-1113, January-February-2018.
Journal URL : http://ijsrcseit.com/CSEIT1831301

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