Low Cost VLSI Architecture for Proposed Adiabatic Offset Encoder and Decoder

Authors

  • Dasari Ratna Kumari  M.Tech-Scholar, Department of ECE, Chintalapudi Engineering College, Guntur, Andhra Pradesh, India
  • G. Srinivasa Rao  Associate Professor, Department of ECE, Chintalapudi Engineering College, Guntur, Andhra Pradesh, India
  • K. Anka Siva Prasad   HOD, Department of ECE, Chintalapudi Engineering College, Guntur, Andhra Pradesh, India

Keywords:

Network on chip[NOC], Adaptive offset[AO], Integrated Circuit [IC]

Abstract

A network-on-chip (NoC) improves the technology and the power dissipated starts to opposed with by the additional elements of the correspond ion subsystem. Sample adaptive encoder architecture has been acquired as a new in-loop filtering block. To get the optimum AO parameters exhaustive operations are required because of the huge amount of samples. In this paper, High speed and low power Proposed Encoder Decoder of rate ½ convolutional coding with a constraint length K = 3 is presented. A high speed it also maintain a low delay in Spartan 6 FPGA. Since the FPGA boards used are different and from that we justified that using both logics together in one Integrated Circuit (IC) we can create a high speed and low power Proposed encoder decoder at the same time with some extra hardware area.

References

  1. Tomas, V., "Decoding of Convolutional Codes Over the Erasure Channel," IEEE Trans. on Information Theory, vol.58, no.1, pp. 90-108, Jan. 2012.
  2. Viterbi AJ. , "Error bounds for convolutional codes and an asymptotically optimum decoding algorithm," IEEE Transactions on Information Theory, Vol. 13, no. 2, pp. 260-269, April 1967.
  3. Bupesh Pandita and Subir K Roy. , "Design and Implementation of Viterbi Decoder Using FPGAs," VLSID '99 Proceedings of the 12th International Conference on VLSI Design, page 611, 1999.
  4. J. Black and T.H. Meng., "A 1-Gb/s, four-state, sliding block Viterbi decoder," IEEE Journal of Solid-State Circuits, Vol. 32 no.6, pp.797-805, 1997.
  5. Boo, F. Arguello, JD Bruguera, R. Doallo, and EL Zapata., "High-performance VLSI architecture for the Viterbi algorithm," IEEE Trans. on communications, Vol. 45, no.2 pp.168-176, 1997.
  6. Collins and F. Pollara., "Memory management in traceback Viterbi decoders," TDA Prog. Rep, pages 42-99, 1989.
  7. Fettweis and H. Meyr., "Parallel Viterbi decoding by breaking the compare select feedback bottleneck," Communications, 201:88, 1988.
  8. Feygin and P. Gulak., "Architectural tradeoffs for survivor sequence memory management in Viterbi decoders," IEEE Transactions on Communications, Vol. 41, no.3, pp. 425- 429, 1993.

IInternational Journal of Scientific Research in Computer Science, Engineering and Information Technology

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Published

2018-02-28

Issue

Volume 3, Issue 1, January-February-2018

Section

Research Articles

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This work is licensed under a Creative Commons Attribution 4.0 International License.

How to Cite

[1]
Dasari Ratna Kumari, G. Srinivasa Rao, K. Anka Siva Prasad , " Low Cost VLSI Architecture for Proposed Adiabatic Offset Encoder and Decoder, IInternational Journal of Scientific Research in Computer Science, Engineering and Information Technology(IJSRCSEIT), ISSN : 2456-3307, Volume 3, Issue 1, pp.1114-1117, January-February-2018.