FPGA Realization of Fault Diagnostic and Fault Tolerant Scheme for Digital Circuits

Authors(2) :-John Kalloor, B. Baskaran

The paper echoes to formulate a sequence for injecting, detecting and healing the random occurrence of stuck at faults in combinational circuits. The philosophy involves the immaculate use of an LFSR to generate interconnect fault patterns in the passage of primary inputs of the circuit on their way to the destination. The theory extends to enjoy the benefits of a checker circuit to identify and ensure the presence of faults in an attempt to transcend the corrective action. It engages the artefacts of digital logic principles to evolve a fault tolerant status for the methodology and facilitates to arrive at the fault free output in the presence of faults. The exercise augurs to annihilate the common types of stuck at faults to enhance the reliability in the use of such circuits. The Modelsim platform espouses to pronounce the reality in realizing the nuances of the design in the procedure and avail the artefacts of an FPGA to demonstrate its practical significance.

Authors and Affiliations

John Kalloor
Department of Electrical and Electronics Engineering, Annamalai University, Chidambaram, Tamil Nadu, India
B. Baskaran
Department of Electrical and Electronics Engineering, Annamalai University, Chidambaram, Tamil Nadu, India

Fault Injection, Fault Tolerance, FPGA, LFSR, Stuck at faults, VHDL

  1. J.C. Baraza, J. Gracia, D. Gil, P.J. Gil, "A prototype of a VHDL-based fault injection tool: Description and Application", Journal of Systems Architecture, vol.47, no. 10, pp. 847–867, 2002.
  2. P. Civera, L. Macchiarulo, M. Rebaudengo, M. S. Reorda and A. Violante, "Exploiting FPGA for Accelerating Fault Injection Experiments," Proceedings of IEEE Online Testing Workshop, Taormina, pp. 9-13, July 2001.
  3. Cristian Constantinescu, "Intermittent Faults in VLSI Circuits", 2nd Workshop on Silicon Errors in Logic - System Effects (SELSE2), April 2006.
  4. Debanjan Ghosh, Raj Sharman, H. Raghav Rao, Shambhu Upadhyaya, "Self-healing systems — Survey and Synthesis", Decision Support Systems, vol. 42, no. 4, pp. 2164-2185, 2006.
  5. S. L. Frenkel and A. V. Pechinkin, "Estimation of Self-Healing Time for Digital Systems under Transient Faults", Informatics and its Applications, vol. 4, no. 3, pp 2-8, 2010.
  6. Goran Lj. Djordjevec, Mile K. Stojcev, Tatjana R. Stankovic, "Approach to Partially Self-Checking Combinational Circuits Design", Microelectronics journal, vol. 35, no. 12, pp. 945-952, December 2004.
  7. Haissam Ziade, Rafic Ayoubi, and Raoul Velazco, "A Survey on Fault Injection Techniques", The International Arab Journal of Information Technology, vol. 1, no. 2, July 2004.
  8. R.V. KShirsagar, R.M. Patrikar, "A New Design Approach For Tolerating Interconnect Faults in Digital Circuits", Proceedings of SPIT-IEEE colloquium and International conference, India, vol. 2, pp. 117-120.
  9. R.V. KShirsagar, R.M. Patrikar, "A Novel Fault Tolerant Design and an Algorithm for tolerating Faults in Digital Circuits", 3rd International Design and Test Workshop, Tunisia, pp. 148-153, December 2008.
  10. P. K. Lala, "Self-Checking and Fault Tolerant Digital Design", Morgan Kaufmann publishers, 2001.
  11. P.K.Lala and B. K.Kumar, "An Architecture for Self-Healing Digital Systems," Journal of Electronic Testing:Theory and Applications, vol. 19, pp. 523-535,2003.
  12. P.K. Lala, B. Kiran Kumar, J.P. Parkerson, "On Self-Healing Digital System Design", Microelectronics Journal, vol. 37, no. 4, pp. 353-362, 2006.
  13. Marc Hunger, Sybille Hellebrand, Alejandro Czutro, Ilia Polian and Bernd Becker, "ATPG-Based Grading of Strong Fault-Secureness", Proceedings of 15th IEEE International On-Line Testing Symposium, Portugal, pp. 269-274, June 2009.
  14. Mitrajit Chatterjee and Dhiraj K. Pradhan, "A BIST Pattern Generator Design for Near-Perfect Fault Coverage", IEEE Transactions on Computers, vol. 52, no. 12, pp. 1543-1548, December 2003.
  15. B. Parrotta, M. Rebaudengo, M. Sonza Reorda, M. Violante, "New techniques for accelerating Fault Injection in VHDL descriptions", Proceedings of 6th IEEE Online Testing Workshop, Palma de Mallorca, pp. 61-66, July 2000.
  16. Petr Fiser, Hana Kubatova, "Pseudorandom Testing – A Study of the Effect of the Generator Type", Acta Polytechnica, vol. 45, no. 2, 2005.
  17. S. R. Seward, P. K. Lala, "Fault Injection in Digital Logic Circuits at the VHDL Level", Proceedings of the 9th IEEE International Conference on On-Line Testing Symposium (IOLTS’03), July 2003.
  18. M.K. Stojcev, G.Lj. Djordjevic, T.R.Stankovic, "Implementation of self- checking two-level combinational logic on FPGA and CPLD circuits", Journal of Microelectronics Reliability, vol. 44, no.1, pp. 173-178, 2004.
  19. Swathi Rudrakshi, Vasujadevi Midasala and S.NagaKishore Bhavanam, "Implementation of FPGA Based Fault Injection Tool (FITO) for Testing Fault Tolerant Designs", IACSIT International Journal of Engineering and Technology, vol.4, no.5, pp. 522-526, October 2012.
  20. Tatjana R. Stankovic, Mile K. Stojcev, and Goran Lj. Djordjevic, "On VHDL Synthesis Of Self Checking Two Level Combinational Circuits", Electrical Energy, vol.17, no. 1, pp. 69-79, April 2004.
  21. Trailokya Nath Sasamal and Anand Mohan, "A Specially Designed Transient Faults Injection Technique at the VHDL Level and Modelling", IJRRAS, vol. 9, no. 2, November 2011.

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Publication Details

Published in : Volume 3 | Issue 1 | January-February 2018
Date of Publication : 2018-02-28
License:  This work is licensed under a Creative Commons Attribution 4.0 International License.
Page(s) : 165-172
Manuscript Number : CSEIT183149
Publisher : Technoscience Academy

ISSN : 2456-3307

Cite This Article :

John Kalloor, B. Baskaran, "FPGA Realization of Fault Diagnostic and Fault Tolerant Scheme for Digital Circuits", International Journal of Scientific Research in Computer Science, Engineering and Information Technology (IJSRCSEIT), ISSN : 2456-3307, Volume 3, Issue 1, pp.165-172, January-February-2018.
Journal URL : http://ijsrcseit.com/CSEIT183149

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