Distributed Packet Buffers for High Bandwidth Switches and Routers

Authors(2) :-Maragoni Mahendar, Pinnapureddy Manasa

High-speed routers rely on well-designed packet buffers that support multiple queues, provide large capacity and short response times. Some researchers suggested combined SRAM/DRAM hierarchical buffer architectures to meet these challenges. However, these architectures suffer from either large SRAM requirement or high time-complexity in the memory management. In this paper, we present scalable, efficient, and novel distributed packet buffer architecture. Two fundamental issues need to be addressed to make this architecture feasible: 1) how to minimize the overhead of an individual packet buffer; and 2) how to design scalable packet buffers using independent buffer subsystems. We address these issues by first designing an efficient compact buffer that reduces the SRAM size requirement by (k - 1)/k. Then, we introduce a feasible way of coordinating multiple subsystems with a load-balancing algorithm that maximizes the overall system performance. Both theoretical analysis and experimental results demonstrate that our load-balancing algorithm and the distributed packet buffer architecture can easily scale to meet the buffering needs of high bandwidth links and satisfy the requirements of scale and support for multiple queues.

Authors and Affiliations

Maragoni Mahendar
Assistant. Professor, Department of CSE, Avanti's Scientific of Technological and Research Academy. Hyderabad, Telangana, India
Pinnapureddy Manasa
M.Tech Student, Department of CSE, Avanti's Scientific of Technological and Research Academy, Hyderabad, Telangana, India

Distributed Packet Buffers, SRAM, DRAM, RTT, Cisco CRS, TCP, HSD

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Publication Details

Published in : Volume 3 | Issue 1 | January-February 2018
Date of Publication : 2018-02-28
License:  This work is licensed under a Creative Commons Attribution 4.0 International License.
Page(s) :
Manuscript Number : CSEIT183172
Publisher : Technoscience Academy

ISSN : 2456-3307

Cite This Article :

Maragoni Mahendar, Pinnapureddy Manasa, "Distributed Packet Buffers for High Bandwidth Switches and Routers", International Journal of Scientific Research in Computer Science, Engineering and Information Technology (IJSRCSEIT), ISSN : 2456-3307, Volume 3, Issue 1, pp., January-February-2018.
Journal URL : http://ijsrcseit.com/CSEIT183172

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