Design and Implementation of a 16 bit ALU in Quantum Dot Cellular Automata

Authors

  • Sreekanth Yedoti  B.Tech Student, Department of ECE, N.B.K.R.Institute of Science and Technology, Nellore, Vidyanagar, Andhra Pradesh India
  • Vinay Kumar Cheekati  B.Tech Student, Department of ECE, N.B.K.R.Institute of Science and Technology, Nellore, Vidyanagar, Andhra Pradesh India
  • P. ValiBasha  B.Tech Student, Department of ECE, N.B.K.R.Institute of Science and Technology, Nellore, Vidyanagar, Andhra Pradesh India

Keywords:

QCA (Quantum dot Cellular Automata), Reversible Gates, ALU (Arithmetic and Logic Unit)

Abstract

The integrated circuits testing is a time consuming task. In order to get shorter test time, some methods need to develop. This paper presents an original method and a practical system design and implementation of Reverse Logic circuits based Arithmetic and Logic unit (ALU). An ALU is a key factor of this computation process. Digital circuits with reversible multiplexer logic give lesser delay when compared to basic logic gates. The analysis of implemented decoder controlled 16 bit ALU, along with vectored multiplexer selection output is presented here. All arithmetic and logic modules are implemented in reversible logics by which delay is reduced along with power consumption. The designs are implemented and verified in QCAD. The paper aims to provide evidence that QCA (Quantum dot Cellular Automata) has potential applications in future Quantum computers, provided that the underlying technology is made feasible. Design has been made using certain combinational circuits by using Majority gate, AND, OR, NOT, X-OR in QCA.

References

  1. CH. Bennett, “Logical Reversibility of Computation”, IBM J.Researchand Development, pp. 525-532, November 1973.
  2. C H Bennett, "Notes on the History of Reversible Computation", IBMJournal of Research and Development,vol. 32, pp. 16-23, 1998.
  3. A Peres, “Reversible logic and quantum computers”, phys. Rev .A,Gen.Phys., vol. 32, no. 6, pp. 32663276, Dec. 1985.
  4. J Rajski, J. Tyszer, M. Kassab, and N. Mukherjee, ``Embedded deterministic test,'' IEEE Trans. Comput.-Aided Des. Integr. Circuits Syst., vol. 23,no. 5, pp. 776_792, May 2004.
  5. Brglez, D. Bryan, K. Kozminski, "Combinational Profiles of sequential benchmark circuits", Proc. IEEE ISCAS, pp. 1929-1934, 1989.
  6. A S Abu-Issa and S. F. Quigley, “Bit-swapping LFSR and scan-chainordering: A novel technique for peak- and average-power reduction in scan-based BIST,” IEEE Trans. Comput.-Aided Des. Integr. Circuits Syst., vol. 28, no. 5, pp. 755–759, May 2009.
  7. V D. Agrawal, C. R. Kime, and K. K. Saluja, “A tutorial on built-in selftest.I. Principles,” IEEE Des. Test Comput., vol. 10, no. 1, pp. 73–82,Mar. 1993.
  8. J Rajski, J. Tyszer, G. Mrugalski, and B. Nadeau-Dostie, “Test generatorwith preselected toggling for low power built-in self-test,” in Proc. Eur.Test Symp., May 2012, pp. 1–6.
  9. Y Sato, S. Wang, T. Kato, K. Miyase, and S. Kajihara, “Low powerBIST for scan-shift and capture power,” in Proc. IEEE 21st Asian TestSymp., Nov. 2012, pp. 173–178.
  10. K Moghaddam, J. Rajski, M. Kassab, and S. M. Reddy, “At-speedscan test with low switching activity,” in Proc. IEEE VLSI Test Symp.,Apr. 2010, pp. 177–182.
  11. A Peres, “Reversible logic and quantum computers”,phys.rev.A,Gen.Phys., vol. 32, no. 6, pp. 32663276, Dec. 1985.
  12. H.G Rangaraju, U. Venugopal, K.N. Muralidhara, K. B. Raja,”Lowpower reversible parallel binary adder / subtractor” arXiv.org/1009.6218,2010.
  13. J.M. Rabaey and M. Pedram, “Low Power Design Methodologies,”Kluwer Academic Publisher, 1997.
  14. T. Toffoli., “Reversible Computing”, Tech memo MIT/LCS/TM-151,MIT Lab for Computer Science 1980.

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Published

2018-04-30

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Section

Research Articles

How to Cite

[1]
Sreekanth Yedoti, Vinay Kumar Cheekati, P. ValiBasha, " Design and Implementation of a 16 bit ALU in Quantum Dot Cellular Automata, IInternational Journal of Scientific Research in Computer Science, Engineering and Information Technology(IJSRCSEIT), ISSN : 2456-3307, Volume 3, Issue 4, pp.1037-1043, March-April-2018.