High Security S-Box Architecture for Triple AES Byte Substitution

Authors(1) :-

In this paper, presents an optimized combinational logic based Rijndael S-Box implementation for the SubByte transformation(S-box) in the Triple Advanced Encryption Standard (AES) algorithm on FPGA. An optimum number of pipeline registers based on Spartan-3E FPGA. The design is fully synthesizable using Verilog HDL. We also conduct a performance analysis and comparison of the proposed architecture with those achieved by existing techniques. The comparison shows that the proposed architecture outperforms the existing techniques in terms of speed and area, efficient implementation of pipelined S-Box was synthesized and implemented using Xilinx ISE v14.3 and Xilinx Spartan-3E .

Authors and Affiliations


M.Tech Scholar, Department of ECE, Sir Visveshwaraiah Institute Of Science & Technology, Madanapalli, Chittoor, Andhra Pradesh, India

Pipelined S-Box, FPGA, AES, Spartan-3E, Triple AES

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Publication Details

Published in : Volume 3 | Issue 4 | March-April 2018
Date of Publication : 2018-04-30
License:  This work is licensed under a Creative Commons Attribution 4.0 International License.
Page(s) : 1067-1072
Manuscript Number : CSEIT1833526
Publisher : Technoscience Academy

ISSN : 2456-3307

Cite This Article :

, "High Security S-Box Architecture for Triple AES Byte Substitution", International Journal of Scientific Research in Computer Science, Engineering and Information Technology (IJSRCSEIT), ISSN : 2456-3307, Volume 3, Issue 4, pp.1067-1072, March-April-2018.
Journal URL : http://ijsrcseit.com/CSEIT1833526

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