High Security S-Box Architecture for Triple AES Byte Substitution

Authors(1) :-

In this paper, presents an optimized combinational logic based Rijndael S-Box implementation for the SubByte transformation(S-box) in the Triple Advanced Encryption Standard (AES) algorithm on FPGA. An optimum number of pipeline registers based on Spartan-3E FPGA. The design is fully synthesizable using Verilog HDL. We also conduct a performance analysis and comparison of the proposed architecture with those achieved by existing techniques. The comparison shows that the proposed architecture outperforms the existing techniques in terms of speed and area, efficient implementation of pipelined S-Box was synthesized and implemented using Xilinx ISE v14.3 and Xilinx Spartan-3E .

Authors and Affiliations

M.Tech Scholar, Department of ECE, Sir Visveshwaraiah Institute Of Science & Technology, Madanapalli, Chittoor, Andhra Pradesh, India

Pipelined S-Box, FPGA, AES, Spartan-3E, Triple AES

  1. Announcing the Advanced Encryption Standard (AES), Federal Information Processing Standards Publication 197, November 2001.
  2. J. Daernen and V.Rijrnen, "Specification of Rijndael," in The Design of Rijndael: AES - The Advanced Encryption Standard, Berlin; New York: Springer-Verlag Berlin Heidel- berg, 2002, pp.31-35
  3. Satoh, S. Morioka, K. Takano and S. Munetoh, "Acompact rijndael hardware architecture with S-box optimization," Springer- Verlag Berlin Heidelberg, 2001.
  4. Yibo Fan, Takeshi Ikenaga, YukiyasuTsunoo, and Satoshi Goto,(2008) “A Lowcost Reconfigurable Architecture for AES Algorithm” proceedings of world academy of science, engineering and technology volume 31 july 2008 ISSN 2070-3740
  5. William Stallings, “Cryptography and Network Security”, Third Edition, www.williamstallings.com/Crypto3e.html
  6. P. Chodowiec, P. Khuon and K. Gaj,(2001) “Fast Implementations of Secret-Key Block Ciphers Using Mixed Inner- and Outer-Round Pipelining,” Proc. ACM/SIGDA Int. Symposium on Field Programmable Gate Arrays, FPGA'01, Monterey, CA.
  7. M. McLoone and J. McCanny,(2001) “Single-chip FPGA Implementation of the Advanced Encryption Standard Algorithm,” in Proc. 11th Int. Conf. Field-Programmable Logicand Applications (FPL 2001), LNSC 2147, pp. 152-161.
  8. N. Sklavos and O. Koufopavlou,(2002) “Architectures and VLSI Implementations of the AES-Proposal Rijndael,” IEEE Trans.on Computers, vol. 51, Issue 12, pp. 1454-1459.
  9. J. H. Shim, D. W. Kim, Y. K. Kang, T.W. Kwon and J. R. Choi,(2002) “A Rijndael Crypto processor Using Shared On-the-fly Key Scheduler,”, pp147-150, 2002.
  10. Refik Sever, A. NeslinI smailoglu, Yusuf C. Tekmen, Murat Askar, BurakOkcan,(2004)”A High speed fpga Implementation of the Rijndael Algorithm” Proceedings of the EUROMICRO Systems on Digital System Design (DSD’04),IEEE, pp.358-362.

Publication Details

Published in : Volume 3 | Issue 4 | March-April 2018
Date of Publication : 2018-04-30
License:  This work is licensed under a Creative Commons Attribution 4.0 International License.
Page(s) : 1067-1072
Manuscript Number : CSEIT1833526
Publisher : Technoscience Academy

ISSN : 2456-3307

Cite This Article :

, "High Security S-Box Architecture for Triple AES Byte Substitution", International Journal of Scientific Research in Computer Science, Engineering and Information Technology (IJSRCSEIT), ISSN : 2456-3307, Volume 3, Issue 4, pp.1067-1072, March-April-2018.
Journal URL : http://ijsrcseit.com/CSEIT1833526

Article Preview