Single Ended 9T Subthreshold SRAM Cell For Low Power Applications Using Dynamic Feedback Control

Authors

  • M. Vijaykanth  M.Tech Student, Department Of ECE, RGM Engineering College,Kurnool, Andhra Pradesh, India
  • N. Nagaraju  Associate Professor, Department Of ECE, RGM Engineering College, Kurnool, Andhra Pradesh, India

Keywords:

Single ended, static noise margin (SNM), static RAM (SRAM), subthreshold, ultralow power.

Abstract

A single-ended nine transistor (9T) Static Random Memory (SRAM) cell is presented in this paper which improves read stability and write ability. The cell employs separate access transistors for read and write operations to eliminate the conflicting design requirement on access transistors. The cell employs feedback loop cut off scheme along with power supply interuption scheme to enhance the write ability. Simulation is done on 180nm standard CMOS technology on Tanner EDA. The proposed single-ended with dynamic feedback control 9T static RAM (SRAM) cell enhances the static noise margin (SNM) for ultralow power supply. Simulation results show that read SNM (RSNM) and write SNM (WSNM) of the proposed cell are 2.77x and 1.12x larger respectively, than those of conventional 8T cell at 1V. Proposed cell consumes 1.4x lesser leakage power than the conventional 8Tcell.

References

  1. K. Roy and S. Prasad, Low-Power CMOS VLSI Circuit Design, 1st ed. New York, NY, USA: Wiley, 2000.
  2. N. Verma and A. P. Chandrakasan, “A 256 kb 65 nm 8T subthreshold SRAM employing sense-amplifier redundancy,” IEEE J. Solid-State Circuits, vol. 43, no. 1, pp. 141–149, Jan. 2008.
  3. C. Kushwah and S. K. Vishvakarma, “Ultra-low power sub-threshold SRAM cell design to improve read static noise margin,” in Progress in VLSI Design and Test (Lecture Notes in Computer Science), vol. 7373. Berlin, Germany: Springer-Verlag, 2012, pp. 139–146.
  4. B. H. Calhoun and A. P. Chandrakasan, “A 256-kb 65-nm sub-threshold SRAM design for ultra-low-voltage operation,” IEEE J. Solid-State Circuits, vol. 42, no. 3, pp. 680–688, Mar. 2007.
  5. C. B. Kushwah, D. Dwivedi, and N. Sathisha, “8T based SRAM cell and related method,” U.S. Patent IN920130 218 US1, May 30, 2013.
  6. J. P. Kulkarni, K. Kim, and K. Roy, “A 160 mV robust Schmitt trigger based subthreshold SRAM,” IEEE J. Solid-State Circuits, vol. 42, no. 10, pp. 2303–2313, Oct. 2007.
  7. C.-H. Lo and S.-Y. Huang, “P-P-N based 10T SRAM cell for low leakage and resilient subthreshold operation,” IEEE J. Solid-State Circuits, vol. 46, no. 3, pp. 695–704, Mar. 2011.
  8. I. Carlson, S. Andersson, S. Natarajan, and A. Alvandpour, “A high density, low leakage, 5T SRAM for embedded caches,” in Proc. 30th Eur. Solid-State Circuits Conf., Sep. 2004, pp. 215–218.
  9. B. Zhai, S. Hanson, D. Blaauw, and D. Sylvester, “A variation-tolerant sub-200 mV 6-T subthreshold SRAM,” IEEE J. Solid-State Circuits, vol. 43, no. 10, pp. 2338–2348, Oct. 2008.
  10. S. A. Tawfik and V. Kursun, “Low power and robust 7T dual-Vt SRAM circuit,” in Proc. IEEE Int. Symp. Circuits Syst., May 2008, pp. 1452–1455.
  11. Ming-Hsien Tu et al., "A single -ended disturb-free 9T sub-threshold SRAM with cross-point data-aware write word-line structure, negative bit-line and adaptive read operation timing tracing, "IEEE J. Solid state circuits, vol. 47, no. 6, pp. 1469-1482, June 2012.
  12. C. Y. Lu et al., “A 0.325 V, 600-kHz, 40-nm 72-kb 9T subthreshold SRAM with aligned boosted write word line and negative write bit line write-assist,” IEEE Trans. Very Large Scale Integr. (VLSI) Syst.,vol. 23, no. 5, pp. 958–962, May 2015
  13. E. Seevinck, F. J. List and J. Lohstroh, “Static noise margin analysis of MOS SRAM cells, "IEEE J. Solid -State Circuits, vol.22, no. 5, pp. 748-754, Oct. 1987.
  14. J. P. Kulkarni, K. Kim, and K. Roy.," A 160 mV robust Schmitt trigger based sub-threshold SRAM," IEEE J. Solid state circuit circuits, vol.42, no.10, pp. 2303-2313 Oct 2007.
  15. S. Ahmad et al., "Single ended Schmitt-trigger based robust low power SRAM cell," IEEE trans. very large scale integration (VLSI) system, vol. 24, no.8, pp. 2634-2642, Aug. 2016.
  16. G. Pasandi, and S. M. Fakhraie, “A 256-kb 9T near-threshold SRAM with 1k cells per bitline and enhanced write and read operations,” IEEE trans IEEE Trans. Very Large Scale Integr. (VLSI) Syst, vol. 23, no.11, pp. 2438-2446, Nov 2015.
  17. S. Akashe, S. Bhushan and S. Sharma, “Modeling and simulation of high level leakage power reduction techniques for 7T SRAM cell design,” Journal of Microelectronics, Electronic Components and Materials, vol. 42, no. 2, 83-87, 2012.

IInternational Journal of Scientific Research in Computer Science, Engineering and Information Technology

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Published

2018-04-30

Issue

Volume 3, Issue 4, March-April-2018

Section

Research Articles

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How to Cite

[1]
M. Vijaykanth, N. Nagaraju, " Single Ended 9T Subthreshold SRAM Cell For Low Power Applications Using Dynamic Feedback Control, IInternational Journal of Scientific Research in Computer Science, Engineering and Information Technology(IJSRCSEIT), ISSN : 2456-3307, Volume 3, Issue 4, pp.1104-1110, March-April-2018.