Single Ended 9T Subthreshold SRAM Cell For Low Power Applications Using Dynamic Feedback Control

Authors(2) :-M. Vijaykanth, N. Nagaraju

A single-ended nine transistor (9T) Static Random Memory (SRAM) cell is presented in this paper which improves read stability and write ability. The cell employs separate access transistors for read and write operations to eliminate the conflicting design requirement on access transistors. The cell employs feedback loop cut off scheme along with power supply interuption scheme to enhance the write ability. Simulation is done on 180nm standard CMOS technology on Tanner EDA. The proposed single-ended with dynamic feedback control 9T static RAM (SRAM) cell enhances the static noise margin (SNM) for ultralow power supply. Simulation results show that read SNM (RSNM) and write SNM (WSNM) of the proposed cell are 2.77x and 1.12x larger respectively, than those of conventional 8T cell at 1V. Proposed cell consumes 1.4x lesser leakage power than the conventional 8Tcell.

Authors and Affiliations

M. Vijaykanth
M.Tech Student, Department Of ECE, RGM Engineering College,Kurnool, Andhra Pradesh, India
N. Nagaraju
Associate Professor, Department Of ECE, RGM Engineering College, Kurnool, Andhra Pradesh, India

Single ended, static noise margin (SNM), static RAM (SRAM), subthreshold, ultralow power.

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Publication Details

Published in : Volume 3 | Issue 4 | March-April 2018
Date of Publication : 2018-04-30
License:  This work is licensed under a Creative Commons Attribution 4.0 International License.
Page(s) : 1104-1110
Manuscript Number : CSEIT1833534
Publisher : Technoscience Academy

ISSN : 2456-3307

Cite This Article :

M. Vijaykanth, N. Nagaraju, "Single Ended 9T Subthreshold SRAM Cell For Low Power Applications Using Dynamic Feedback Control", International Journal of Scientific Research in Computer Science, Engineering and Information Technology (IJSRCSEIT), ISSN : 2456-3307, Volume 3, Issue 4, pp.1104-1110, March-April-2018.
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