High Performance Scalable Deep Learning Accelerator Unit on FPGA

Authors(2) :-V. Jhansi, Dr. Chandrasekhar

The deep learning network the size of the networks becomes increasingly large scale due to the demands of the practical applications .The DLAU architecture can be configured to operate different sizes of tile data to leverage the trade-offs between speedup and hardware costs. Consequently the FPGA based accelerator is more scalable to accommodate different machines. The DLAU includes three pipelined processing units, which can be reused for large scale neural networks. High performance implementation of deep learning neural network is maintain the low power cost and less delay .in this work is we are done the samples of network signals which attain data optimization, upgraded the speed.

Authors and Affiliations

V. Jhansi
M.Tech Student, Department of ECE, S.V. College of Engineering, Tirupati, India
Dr. Chandrasekhar
Professor, Department of ECE, S.V. College of Engineering,Tirupati, India

DLAU, Neural network ,Deep learning, Accelerator.

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Publication Details

Published in : Volume 3 | Issue 5 | May-June 2018
Date of Publication : 2018-06-30
License:  This work is licensed under a Creative Commons Attribution 4.0 International License.
Page(s) : 815-819
Manuscript Number : CSEIT1835177
Publisher : Technoscience Academy

ISSN : 2456-3307

Cite This Article :

V. Jhansi, Dr. Chandrasekhar, "High Performance Scalable Deep Learning Accelerator Unit on FPGA", International Journal of Scientific Research in Computer Science, Engineering and Information Technology (IJSRCSEIT), ISSN : 2456-3307, Volume 3, Issue 5, pp.815-819, May-June-2018.
Journal URL : http://ijsrcseit.com/CSEIT1835177

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