Design of Weighted Pseudorandom Test Pattern Generation for BIST Implementation Using Low Power

Authors(2) :-Arva Sreelakshmi, G. Jagadeeshwar Reddy

This paper presents, the generation of significant power droop (PD) during at-speed test performed by Logic Built-In Self Test (LBIST) is a serious concern for modern ICs. In fact, the PD originated during test may delay signal transitions of the circuit under test (CUT): an effect that may be erroneously recognized as delay faults, with consequent erroneous generation of test fails and increase in yield loss A new low-power (LP) scan-based built-in self test (BIST) technique is proposed based on weighted pseudorandom test pattern generation and reseeding along with. A new LP scan architecture is proposed, which supports both pseudorandom testing and deterministic BIST. During at-speed test of high performance sequential ICs using scan-based Logic BIST, the IC activity factor (AF) induced by the applied test vectors is significantly higher than that experienced during its infield operation. Consequently, power droop (PD) may take place during both shift and capture phases, which will slow down the circuit under test (CUT) signal transitions. At capture, this phenomenon is likely to be erroneously recognized as due to delay faults. As a result, a false test fail may be generated, with consequent increase in yield loss. In this paper, along with pseudorandom testing and deterministic BIST proposes another approaches to reduce the PD generated at capture during at-speed test of circuits with scan-based Logic .During the pseudorandom testing Phase, by disabling a part of scan chains an LP weighted random test pattern generation scheme is achieved. During the deterministic BIST phase, the design-for-testability architecture by slight modification of LFSR and fault coverage is increases and power is reduced by this approaches.

Authors and Affiliations

Arva Sreelakshmi
M.Tech student, Department Of ECE, Vaagdevi Institute of Technology & Sciences, Proddatur, Andhra Pradesh, India
G. Jagadeeshwar Reddy
Professor, Department Of ECE, Vaagdevi Institute of Technology & Sciences, Proddatur, Andhra Pradesh, India

Built in Self-Test, LFSR, Low power, Circuit under test.

  1. Prof. A. S. Abu-Issa and S. F. Quigley, "Bit-swapping LFSR and scan-chain ordering: A novel technique for peak- and average-power reduction in scan-based BIST," IEEE Trans. Compute.-Aided Des. Integr. Circuits Syst., vol. 28, no. 5, pp. 755–759, May 2009.
  2. V. D. Agrawal, C. R. Kime, and K. K. Saluja, "A tutorial on built-in selftest. I. Principles," IEEE Des. Test Comput., vol. 10, no. 1, pp. 73–82, Mar. 1993.
  3. A. Al-Yamani, N. Devta-Prasanna, E. Chmelar, M. Grinchuk, and A. Gunda, "Scan test cost and power reduction through systematic scan Reconfiguration," IEEE Trans. Compute.-Aided Des. Integr. Circuits Syst., vol. 26, no. 5, pp. 907–918, May 2007.
  4. Synopsys. ASTRO: Advanced Place-and-Route Solution for SoC Design, accessed on Mar. 1, 2015. [Online].Available:
  5. S. Banerjee, D. R. Chowdhury, and B. B. Bhattacharya, "An efficient scan tree design for compact test pattern set," IEEE Trans. Compute.-Aided Des. Integr. Circuits Syst., vol. 26, no. 7, pp. 1331–1339, Jul. 2007.
  6. P. H. Bardell, W. H. McAnney, and J. Savir, Built in Test for VLSI: Pseudorandom Techniques. New York, NY, USA: Wiley, 1987.
  7. N. Z. Basturkmen, S. M. Reddy, and I. Pomeranz, "A low power pseudorandom BIST technique," J. Electron. Test., Theory Appl., vol. 19, no. 6, pp. 637–644, Dec. 2003.
  8. M. L. Bushnell and V. D. Agrawal, Essentials of Electronic Testing. Norwell, MA, USA: Kluwer, 2000.
  9. M. Chatterjee and D. K. Pradhan, "A BIST pattern generator design for near-perfect fault coverage," IEEE Trans. Compute., vol. 52, no. 12, pp. 1543–1558, Dec. 2003.
  10. M. Filipek et al., "Low-power programmable PRPG with test compression capabilities," IEEE Trans. Very Large Scale Integr. (VLSI) Syst.,
  11. P. Girard, et al., "A Modified Clock Scheme for a Low Power BIST Test Pattern Ggenerator" in Proc. of IEEE VLSI Test Symp., 2001, pp. 306 – 311.
  12. S. M. Reddy, et al., "A Low Power Pseudo-Random BIST Technique", in Proc. of IEEE Int.l On-Line Testing Workshop, 2002, pp. 140 – 144.
  13. M.Tehranipoor, M. Nourani, N. Ahmed, "Low Transition LFSR for BIST-Based Applications", in Proc. of 14th Asian T1est Symp., 2005, pp. 138 – 143.
  14. Y. Huang, X. Lin, "Programmable Logic BIST for At-Speed Test", in Proc. of 16th Asian Test Symp., 2007, pp. 295 – 300.
  15. I. Polian, A. Czutro, S. Kundu, B. Becker, "Power Droop Testing", IEEE Design & Test of Computers, 24(3), 2007, pp. 276 – 284.
  16. M. Nourani, et al., "Low-Transition Test Pattern Generation for BIST-Based Applications", IEEE Trans. on Comp., Vol. 57, No. 3, March 2008, pp. 303 – 315. vol. 23, no. 6, pp. 1063–1076, Jun. 2015.

Publication Details

Published in : Volume 3 | Issue 5 | May-June 2018
Date of Publication : 2018-06-30
License:  This work is licensed under a Creative Commons Attribution 4.0 International License.
Page(s) : 1016-1022
Manuscript Number : CSEIT1835197
Publisher : Technoscience Academy

ISSN : 2456-3307

Cite This Article :

Arva Sreelakshmi, G. Jagadeeshwar Reddy, "Design of Weighted Pseudorandom Test Pattern Generation for BIST Implementation Using Low Power", International Journal of Scientific Research in Computer Science, Engineering and Information Technology (IJSRCSEIT), ISSN : 2456-3307, Volume 3, Issue 5, pp.1016-1022, May-June-2018.
Journal URL :

Follow Us

Contact Us