Design of Weighted Pseudorandom Test Pattern Generation for BIST Implementation Using Low Power

Abstract

This paper presents, the generation of significant power droop (PD) during at-speed test performed by Logic Built-In Self Test (LBIST) is a serious concern for modern ICs. In fact, the PD originated during test may delay signal transitions of the circuit under test (CUT): an effect that may be erroneously recognized as delay faults, with consequent erroneous generation of test fails and increase in yield loss A new low-power (LP) scan-based built-in self test (BIST) technique is proposed based on weighted pseudorandom test pattern generation and reseeding along with. A new LP scan architecture is proposed, which supports both pseudorandom testing and deterministic BIST. During at-speed test of high performance sequential ICs using scan-based Logic BIST, the IC activity factor (AF) induced by the applied test vectors is significantly higher than that experienced during its infield operation. Consequently, power droop (PD) may take place during both shift and capture phases, which will slow down the circuit under test (CUT) signal transitions. At capture, this phenomenon is likely to be erroneously recognized as due to delay faults. As a result, a false test fail may be generated, with consequent increase in yield loss. In this paper, along with pseudorandom testing and deterministic BIST proposes another approaches to reduce the PD generated at capture during at-speed test of circuits with scan-based Logic .During the pseudorandom testing Phase, by disabling a part of scan chains an LP weighted random test pattern generation scheme is achieved. During the deterministic BIST phase, the design-for-testability architecture by slight modification of LFSR and fault coverage is increases and power is reduced by this approaches.