High speed and Area Efficient Rounding Based Approximate Multiplier for Digital Signal Processing

Authors(2) :-B Chandravathi, D Nagaraju

Approximate computing can decrease the design complexity with an increase in performance and power efficiency for error resilient applications. This brief deals with a new design approach for approximation of multipliers. Energy consumption is one of the key factors for various processing application like DSP, ASIC and FPGA. The main aim of this project is to approximate the multiplying operation. The approach is to round the operands to the nearest exponent of two. Through this way the speed is increased and energy consumption is reduced by reducing computational operations at the price of a small error. In this way, the computational intensive part of the multiplication was omitted improving speed and energy consumption at the price of a small error. The proposed approach was applicable to both signed and unsigned multiplications. Three hardware implementations of the approximate multiplier including one for the unsigned and two for the signed operations were discussed. The proposed 8-bit RoBA multiplier for signed and unsigned multiplication offers better efficiency in energy consumption .Furthermore, the area is compacted well besides it provides reduction in Power Delay Area (PDA).

Authors and Affiliations

B Chandravathi
M.Tech Student, Department of ECE, Vagdevi Institute of Technology and Science , Proddatur, India
D Nagaraju
Assistant Professor, Department of ECE, Vagdevi Institute of Technology and Science , Proddatur, India

Round-off, Approximate, Energy consumption Rounding Based Approximate Multiplier (RoBA), Power Delay Product (PDA).

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Publication Details

Published in : Volume 3 | Issue 5 | May-June 2018
Date of Publication : 2018-06-30
License:  This work is licensed under a Creative Commons Attribution 4.0 International License.
Page(s) : 1075-1081
Manuscript Number : CSEIT1835204
Publisher : Technoscience Academy

ISSN : 2456-3307

Cite This Article :

B Chandravathi, D Nagaraju, "High speed and Area Efficient Rounding Based Approximate Multiplier for Digital Signal Processing ", International Journal of Scientific Research in Computer Science, Engineering and Information Technology (IJSRCSEIT), ISSN : 2456-3307, Volume 3, Issue 5, pp.1075-1081, May-June-2018.
Journal URL : http://ijsrcseit.com/CSEIT1835204

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