High speed and Area Efficient Rounding Based Approximate Multiplier for Digital Signal Processing
Keywords:
Round-off, Approximate, Energy consumption Rounding Based Approximate Multiplier (RoBA), Power Delay Product (PDA).Abstract
Approximate computing can decrease the design complexity with an increase in performance and power efficiency for error resilient applications. This brief deals with a new design approach for approximation of multipliers. Energy consumption is one of the key factors for various processing application like DSP, ASIC and FPGA. The main aim of this project is to approximate the multiplying operation. The approach is to round the operands to the nearest exponent of two. Through this way the speed is increased and energy consumption is reduced by reducing computational operations at the price of a small error. In this way, the computational intensive part of the multiplication was omitted improving speed and energy consumption at the price of a small error. The proposed approach was applicable to both signed and unsigned multiplications. Three hardware implementations of the approximate multiplier including one for the unsigned and two for the signed operations were discussed. The proposed 8-bit RoBA multiplier for signed and unsigned multiplication offers better efficiency in energy consumption .Furthermore, the area is compacted well besides it provides reduction in Power Delay Area (PDA).
References
- Mitchell, J. N. (1962). Computer multiplication and division using binary logarithms. IRE Trans. Electron. Comput. EC-11: 512–517.
- H. R. Mahdiani, A. Ahmadi, S. M. Fakhraie, and C. Lucas, “Bio-inspired imprecise computational blocks for efficient VLSI implementation of soft-computing applications,” IEEE Trans. Circuits Syst. I, Reg. Papers, vol. 57, no. 4, pp. 850– 862, Apr. 2010
- R. Venkatesan, A. Agarwal, K. Roy, and A.Raghunathan, “MACACO: Modeling and analysis of circuits for approximate computing,” in Proc. Int. Conf. Comput.-Aided Design, Nov. 2011, pp. 667– 673.
- F. Farshchi, M. S. Abrishami, and S. M. Fakhraie, “New approximate multiplier for low power digital signal processing,” in Proc. 17th Int. Symp. Comput. Archit. Digit. Syst. (CADS), Oct. 2013, pp. 25–30.
- P. Kulkarni, P. Gupta, and M. Ercegovac, “Trading accuracy for power with an under designed multiplier architecture,” in Proc. 24th Int. Conf. VLSI Design, Jan. 2011, pp. 346–351.
- V. Gupta, D. Mohapatra, A. Raghunathan, and K.Roy, “Low- power digital signal processing using approximate adders,” IEEE Trans. Comput.-Aided Design Integr. Circuits Syst., vol. 32, no. 1, pp. 124– 137, Jan. 2013.
- M. Alioto, “Ultra-low power VLSI circuit design demystified and explained: A tutorial,” IEEE Trans. Circuits Syst. I, Reg. Papers, vol. 59, no. 1, pp. 3–29, Jan. 2012.
- K.Y. Kyaw, W. L. Goh, and K. S. Yeo, “Low-power high-speed multiplier for error tolerant application,” in Proc. IEEE Int. Conf. Electron Devices Solid-State Circuits (EDSSC), Dec. 2010, pp. 1–4.
- A.B. Kahng and S. Kang, “Accuracy-configurable adder for approximate arithmetic designs,” in Proc. 49th Design Autom. Conf. (DAC), Jun. 2012, pp. 820–825.
- Samir Palnitkar, Verilog HDL: A Guide to Digital Design and Synthesis, Second edition, Prentice-hall PTR, 2003.
- R.Dubey , J.Jain, “An efficient Processing by Using Kogge Stone High Speed technique,” in proc.
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