Design and Implementation of ALU Using Reversible Decoder Logic

Authors(2) :-Y. Jyosthna, B. venkatesu

Digital system implemented by using conventional gates or irreversible logics like AND and OR gates dissipates a major amount of energy in the form of bits which gets erased during logical operations. This problem of energy loss can be solving by using reversible logic circuits in place of conventional circuits. The Irreversible logic is replaced by reversible logic to decrease the Power dissipation. Reversible logic functions have emerged as an important research area. Implementing the reversible logic has the advantages of reducing gate counts, garbage outputs as well as constant inputs. In today’s world ALU is one of the very important part of any system having many applications in computers, cell phones, etc. Addition, subtraction operations are realized using reversible by using reversible gates. Reversible decoder is designed using Fredkin gates with minimum Quantum cost.. The proposed method require less complexity, less hardware, minimum number of gates, minimum number of garbage inputs and minimum number of constant inputs than existing methods. The proposed circuits will be simulated using ModelSim simulator and implemented in Xilinx.

Authors and Affiliations

Y. Jyosthna
M.tech student, ECE department, Shree Institute of Technological Education, Peddanjimedu, Andhra Pradesh, India
B. venkatesu
Assistant professor, ECE department, Shree Institute of Technological Education, Peddanjimedu, Andhra Pradesh, India

Reversible Logic, Quantum Computing, Garbage Outputs, Full Adder, Full Subtractor, Decoder.

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Publication Details

Published in : Volume 3 | Issue 6 | July-August 2018
Date of Publication : 2018-07-30
License:  This work is licensed under a Creative Commons Attribution 4.0 International License.
Page(s) : 280-287
Manuscript Number : CSEIT1835268
Publisher : Technoscience Academy

ISSN : 2456-3307

Cite This Article :

Y. Jyosthna, B. venkatesu, "Design and Implementation of ALU Using Reversible Decoder Logic", International Journal of Scientific Research in Computer Science, Engineering and Information Technology (IJSRCSEIT), ISSN : 2456-3307, Volume 3, Issue 6, pp.280-287, July-August-2018.
Journal URL : http://ijsrcseit.com/CSEIT1835268

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