Design and Implementation of Reconfigurable Approximation Technique for Arithmetic Unit

Authors

  • I. S. Priya  M. Tech Student, Head Of The Department, ECE Shree Institute of Technical Education, Tirupathi, India
  • B. Venkatesh  Assistant Professor & Head Of The Department, ECE Shree Institute of Technical Education, Tirupathi, India

Keywords:

Approximate circuits, approximate computing, low power design, quality configurable.

Abstract

The research community in the last few years from the field of approximate computing has received significant attention, particularly in the context of different signal processing. Image and video compression algorithms such as JPEG, MPEG and so on, which can be exploited to realize highly power efficient implementations of these algorithms. However, existing approximate architectures typically fix the level of hardware approximations statically and are not adaptive to input data. This project addresses this issue by proposing a reconfigurable approximate for MPEG encoders that optimizes power consumption with the aim of maintaining a particular peak signal-to noise ratio threshold for any video. We propose two heuristics for automatically tuning the approximation degree of the RABs in these two modules during runtime based on the Characteristics of each individual video. The proposed architecture of this paper analysis the logic size, area and power consumption using Xilinx 14.3.

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Published

2018-09-30

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Section

Research Articles

How to Cite

[1]
I. S. Priya, B. Venkatesh, " Design and Implementation of Reconfigurable Approximation Technique for Arithmetic Unit , IInternational Journal of Scientific Research in Computer Science, Engineering and Information Technology(IJSRCSEIT), ISSN : 2456-3307, Volume 3, Issue 7, pp.36-39, September-October-2018.