Performance Analysis of Fully Differential Double Tail Dynamic Comparator
Keywords:
Comparator, Differential Dynamic Comparator (DDC), Fully Differential Double Tail Dynamic Comparator (FDDTDC), Analog to Digital Converters (ADCs), Propagation delay, Offset Voltage, Power Dissipation.Abstract
This paper presents a novel fully differential double tail dynamic comparator that exhibits lower offset voltage than the conventional dynamic comparators. This paper comprises a novel fully differential double tail high performance comparator suitable for low-voltage low-power applications. A fully differential double tail comparator has been designed to meet the necessity of low offset voltage for optimum power with high speed. The expression for the calculation of the offset voltage of the proposed comparator is derived. These expressions corroborate previously stated results with analytical support as well as providing useful insight for the design of fully differential double tail dynamic comparator by analyzing the influence of each transistor pair individually. Transistor mismatch analysis is carried out for offset voltage to fully explore the trade-offs in the design of comparator. In proposed comparator offset voltage is significantly reduced for optimum power. Authors have proposed novel architecture of dynamic voltage comparator which is differential and double tail and verified the architecture by simulation in 180nm CMOS technology with ±0.9V supply. The Post-layout simulation results illustrates that a comparator designed with the proposed techniques is 45% faster, and 30% more power efficient and exhibits 91% low offset as compared with conventional comparator, which is the fastest among the conventional comparators.
References
- R. Jecob Baker, Harry W. Li, David E. Boyce, “CMOS Circuit Design, Layout and Simulation”, IEEE Press Series on Microelectronic Systems, pp.685-699, 1997.
- Phillip E. Allen, Douglas R. Holberg, “CMOS Analog Circuit Design”, Oxford University Press, Second Edition, pp.439-488, 2002.
- L. Sumanen; M. Waltari; K. Halonen, “A mismatch insensitive CMOS dynamic comparator for pipeline A/D converters”,. 7th IEEE International Conference on Electronics, Circuits and Systems ICECS 2000, vol.1, pp. 32 – 35, Dec. 2000.
- L. Sumanen, M. Waltari, V. Hakkarainen, K. Halonen, "CMOS Dynamic Comparators for Pipeline A/D Converters," IEEE ISCAS, vol. 5, pp. 157-160, May 2002.
- T. W. Matthews, P. L. Heedley, "A Simulation Method for Accurately Determining DC and Dynamic Offset in Comparators," IEEE MWSCAS, pp. 1815-1818, Aug. 2005.
- P. Uthaichana, E. Leelarasmee, “Low Power CMOS Dynamic Latch Comparators”, TENCON 2003, Conference on Convergent Technologies for the Asia-Pacific Region, pp605-608 Vol.2 Oct 2003.
- Vipul Katyal, Randall L. Geiger and Degang J. Chen, “A New High Precision Low Offset Dynamic Comparator for High Resolution High Speed ADCs”, IEEE Asia Pacific Conference on Circuits and Systems, 2006 (APCCAS 2006) pp.5-8, Dec.2006.
- Jun He, Sanyi Zhan, Degang Chen, Randall L. Geiger, “A Simple and Accurate Method to Predict Offset Voltage in Dynamic Comparators”, IEEE International Symposium on Circuits and Systems, 2008, pp. 1934-1937, May. 2008.
- Jun He, Sanyi Zhan, Degang Chen, Randall L. Geiger, "Analyses of Static and Dynamic Random Offset Voltages in Dynamic Comparators", IEEE Transactions on Circuits and Systems I: Regular Papers, ISSN 1549-8328 ISSN 1549-8328, vol. 56, pp. 911-919, May. 2009,.
- Heung Jun Jeon, Yong-Bin Kim, “A Low-offset High-speed Double-tail Dual-rail Dynamic Latched Comparator”, GLSVLSI '10 Proceedings of the 20th symposium on Great lakes symposium on VLSI, pp. 45-48, Sep. 2010.
- Heung Jun Jeon and Yong-Bin Kim, “A Novel Low Power, Low Offset, and High Speed CMOS Dynamic Latched Comparator”, Analog Intergrated Circuit Signal Processing, July. 2011.
- Heung Jun Jeon, Yong-Bin Kim, “A CMOS Low Power Low Offset and High-Speed Fully Dynamic Latched Comparator” , IEEE SOC International Conference (SOCC), pp. 285-288, Sep. 2010.
- S. Babayan-Mashhadi, R. Lotfi, “Analysis and Design of a Low-Voltage Low-Power Double-Tail Comparator” IEEE Transactions on Very Large Scale Integration (VLSI) Systems, (Volume:22 , Issue: 2 ) pp. 343 – 352, Feb. 2014.
- M. Hassanpourghadi, M. Zamani and M. Sharifkhani, “A Low-Power Low-Offset Dynamic Comparator for Analog to Digital Converters”, Microelectronis Journal, Elsevier, pp.256-262. Feb 2014.
- Dhanisha N. Kapadia, Priyesh P. Gandhi “Design and Comparative Analysis of Differential Current Sensing Comparator in Deep Sub -Micron Region”. Proceedings of2013 IEEE Conference on Information and Communication Technologies, pp. 21-25, April. 2013..
- Dhanisha N. Kapadia, Priyesh P. Gandhi, “Implemnation of CMOS Charge Sharing Dynamic Latch Comparator in 130nm and 90nm Technologies”. Proceedings of 2013 IEEE Conference on Information asnd Communication, pp. 16-20, April. 2013.
- IIi Shairah Abdul Halim, Nurul Aisyah Nadiah Binti Zainal Abidin, A’zraa Afhzan Ab Rahim, “Low Power CMOS Charge Sharing Dynamic Latch Comparator using 0.18µm Technology”, IEEE Regional Symposium on Micro and Nanoelectronics (RSM), pp.156-160,Sep.2011.
- M. J. Taghizadeh Marvast, M. A. Mohd Ali, “High Speed Comparator for Flash ADC and UWB Application in 130nm CMOS Technology”, IEEE Conference on Signal and Image Processing Applications, pp. 402-405, 2009.
- Nurul Iffah Mohamad Azizi, Siti Hawa Ruslan, “Design of A Low Power 0.25µm CMOS Compartor for Sigma-Delta Analog -to- Digital Converter”, IEEE Student Conference on Research and Development (SCOReD), pp.638-642, Dec. 2015.
- Dinanath N. Donadkar, Sheetal U. Bhandari, “Review on Comparator Design for High Speed ADCs” IEEE International Conference on Computing Communication Control and Automation, pp. 974-978, Feb. 2015.
- Samaneh Babayan-Mashhadi, Mojtaba Daliri, Reza Lotfi, “Analysis of Power in Dynamic Comparators”, 21st Iranian Conference on Electrical Engineering (ICEE), 2013 pp.1-4, May.2013.
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