Low-Power Approximate Unsigned and Signed Multipliers with Configurable Error Recovery

Dr. K. Nagi Reddy; K. Ruchitha; B. Sai Srinivas; D. Venu, K. Vinay

doi:10.32628/CSEIT2410311

Authors

Dr. K. Nagi Reddy Professor of ECE, NBKR Institute of Science & Technology, Vidyanagar, Nellore, Andhra Pradesh, India Author
K. Ruchitha NBKR Institute of Science & Technology, Vidyanagar, Nellore, Andhra Pradesh, India Author
B. Sai Srinivas NBKR Institute of Science & Technology, Vidyanagar, Nellore, Andhra Pradesh, India Author
D. Venu, K. Vinay Professor of ECE, NBKR Institute of Science & Technology, Vidyanagar, Nellore, Andhra Pradesh, India Author

DOI:

https://doi.org/10.32628/CSEIT2410311

Keywords:

Multiplier, Digital Signal Processing, Digital Systems, Carry Propagation Adder

Abstract

In the field of Digital Signal Processing and similar applications, Approximate circuits are being explored as a means to enhance performance and energy efficiency by sacrificing a degree of accuracy. Within these circuits, Multipliers play a crucial role and are being investigated for their potential impact on overall system optimization. In this paper, a novel approximate multiplier with a low power consumption and a short critical path is proposed for high-performance DSP applications. This multiplier leverages a newly designed approximate adder that limits its carry propagation to the nearest neighbours for fast partial product accumulation. Different levels of accuracy can be achieved by using either OR gates or the proposed approximate adder in a configurable error recovery. The multipliers using these two error reduction strategies are referred to as Approximate Multiplier 1 (AM1) and Approximate Multiplier 2 (AM2), respectively. Both AM1 and AM2 have a low mean error distance, i.e., most of the errors are not significant in magnitude. Compared with a Unsigned multiplication multiplier, with the signed multiplication. The signed multiplication tends to have lower power consumption is observed. By utilizing an appropriate error recovery, the proposed approximate multipliers achieve similar processing accuracy as traditional exact multipliers, but with significant improvements in power.

Downloads

Download data is not yet available.

References

Honglan Jiang*, Student Member, IEEE, Cong Liu*, Fabrizio Lombardi, Fellow, IEEE and Jie Han, Senior Member, IEEE

S. L. Lu, “Speeding up processing with approximation circuits,” Computer, vol. 37, no. 3, pp. 67–73, 2004. DOI: https://doi.org/10.1109/MC.2004.1274006

A. K. Verma, P. Brisk, and P. Ienne, “Variable latency speculative addition: A new paradigm for arithmetic circuit design,” in Proceedings of the conference on Design, automation and test in Europe. ACM, 2008, pp. 1250–1255. DOI: https://doi.org/10.1145/1403375.1403679

N. Zhu, W. L. Goh, and K. S. Yeo, “An enhanced low-power highspeed adder for error-tolerant application,” in Proceedings of the 2009 12th International Symposium on Integrated Circuits. IEEE, 2009, pp. 69–72.

H. R. Mahdiani, A. Ahmadi, S. M. Fakhraie, and C. Lucas, “Bioinspired imprecise computational blocks for efficient vlsi implementation of soft-computing applications,” IEEE Transactions on Circuits and Systems I: Regular Papers, vol. 57, no. 4, pp. 850–862, 2010. DOI: https://doi.org/10.1109/TCSI.2009.2027626

V. Gupta, D. Mohapatra, S. P. Park, A. Raghunathan, and K. Roy, “Impact: imprecise adders for low-power approximate computing,” in International Symposium on Low Power Electronics and Design (ISLPED). IEEE, 2011, pp. 409–414. DOI: https://doi.org/10.1109/ISLPED.2011.5993675

A. B. Kahng and S. Kang, “Accuracy-configurable adder for approximate arithmetic designs,” in Proceedings of the 49th Annual Design Automation Conference. ACM, 2012, pp. 820–825. DOI: https://doi.org/10.1145/2228360.2228509

K. Du, P. Varman, and K. Mohanram, “High performance reliable variable latency carry select addition,” in Design, Automation Test in Europe Conference Exhibition (DATE), 2012, pp. 1257–1262.

J. Liang, J. Han, and F. Lombardi, “New metrics for the reliability of approximate and probabilistic adders,” Computers, IEEE Transactions on, vol. 62, no. 9, pp. 1760–1771, 2013. DOI: https://doi.org/10.1109/TC.2012.146

J. Huang, J. Lach, and G. Robins, “A methodology for energy-quality trade off using imprecise hardware,” in Proceedings of the 49th Annual Design Automation Conference. ACM, 2012, pp. 504–509. DOI: https://doi.org/10.1145/2228360.2228450

J. Miao, K. He, A. Gerstlauer, and M. Orshansky, “Modelling and synthesis of quality-energy optimal approximate adders,” in Proceedings of the International Conference on Computer-Aided Design. ACM, 2012, pp. 728–735. DOI: https://doi.org/10.1145/2429384.2429542

R. Venkatesan, A. Agarwal, K. Roy, and A. Raghunathan, “Macaco: Modelling and analysis of circuits for approximate computing,” in Proceedings of the International Conference on Computer-Aided Design. IEEE Press, 2010, pp. 667–673. DOI: https://doi.org/10.1109/ICCAD.2011.6105401

H. Jiang, C. Liu, L. Liu, F. Lombardi, and J. Han, “A review, classification and comparative evaluation of approximate arithmetic circuits,” ACM Journal on Emerging Technologies in Computing Systems, vol. 13, no. 4, p. 60, 2017 DOI: https://doi.org/10.1145/3094124

B. Parhami, Computer arithmetic. Oxford university press, 2000.

P. Kulkarni, P. Gupta, and M. D. Ercegovac, “Trading accuracy for power in a multiplier architecture,” Journal of Low Power Electronics, vol. 7, no. 4, pp. 490–501, 2011. DOI: https://doi.org/10.1166/jolpe.2011.1157