Design and Implementation of Modified Vedic Multiplier in FPGA Design Using Zero Knowledge Verification Key
Keywords:
Vedic Multiplier; Watermarking; Zero Knowledge Algorithm; FPGA,AHL, Razor Flipflop;Abstract
Watermarking as a novel intellectual property protection technique, here the 16Bit Vedic Multiplier is used and it is designed by using AHL circuit and Razor Flip-flop for reducing delay of operation. This modified Vedic multiplier is implemented in FPGA (Xilinx Vertex – 5 Board). With the use of Zero knowledge verification protocol, the FPGA’s Intellectual Property are protect from infringement. This project proposes a new watermarking detection technique based on chaos-based zero-knowledge interaction with Digital signature. The digital signature is watermarked and it is used as a verification key. This digital signature is retrieved by zero knowledge verification protocol. The zero knowledge algorithms is a cryptography based network security algorithm. This protocol is used to resist the sensitive information leakage and embedding attack and is thus robust to the cheating from the prover, verifier, or third party. The result may get better robustness than the most recent related literature.
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