Design a Finite Field Multiplier for Novel Cryptography

Abstract

The process to develop a federal information processing standard for the advanced encryption algorithm to replace the data encryption standard. In this paper, we proposed an efficient VLSI architecture for advanced encryption standard design methodology in order to provide a high-speed and effective cryptographic operation. High-performance and fast implementation of proposed multiplication is applied to cryptographic systems. The internal multiplier contains three stages of operations. They are pre-processing stage, carry generation stage, post-processing stage. The pre-processing stage concentrate on propagate and generate, carry generation stage focuses on carry generation and post-processing stage focuses on final result. In this paper, we propose efficient and high speed architectures to implement cryptography using proposed multiplier. Cryptography is the operation in wireless communication between transmissions and receiving of data, the secured data is communicated in an unsecured channel between transmitter and receiver with high security. At the transmitter side the original data is converted in to secured sequence and at the receiver side the secured sequence is converted in to original data sequence. Our proposed multiplier is used in that conversion and by using this converter we are designing a cryptography application.