High Security S-Box Architecture for Triple AES Byte Substitution
Keywords:
Pipelined S-Box, FPGA, AES, Spartan-3E, Triple AESAbstract
In this paper, presents an optimized combinational logic based Rijndael S-Box implementation for the SubByte transformation(S-box) in the Triple Advanced Encryption Standard (AES) algorithm on FPGA. An optimum number of pipeline registers based on Spartan-3E FPGA. The design is fully synthesizable using Verilog HDL. We also conduct a performance analysis and comparison of the proposed architecture with those achieved by existing techniques. The comparison shows that the proposed architecture outperforms the existing techniques in terms of speed and area, efficient implementation of pipelined S-Box was synthesized and implemented using Xilinx ISE v14.3 and Xilinx Spartan-3E .
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