Design and Implementation of ALU Using Reversible Decoder Logic

Authors

  • Y. Jyosthna  M.tech student, ECE department, Shree Institute of Technological Education, Peddanjimedu, Andhra Pradesh, India
  • B. venkatesu  Assistant professor, ECE department, Shree Institute of Technological Education, Peddanjimedu, Andhra Pradesh, India

Keywords:

Reversible Logic, Quantum Computing, Garbage Outputs, Full Adder, Full Subtractor, Decoder.

Abstract

Digital system implemented by using conventional gates or irreversible logics like AND and OR gates dissipates a major amount of energy in the form of bits which gets erased during logical operations. This problem of energy loss can be solving by using reversible logic circuits in place of conventional circuits. The Irreversible logic is replaced by reversible logic to decrease the Power dissipation. Reversible logic functions have emerged as an important research area. Implementing the reversible logic has the advantages of reducing gate counts, garbage outputs as well as constant inputs. In today’s world ALU is one of the very important part of any system having many applications in computers, cell phones, etc. Addition, subtraction operations are realized using reversible by using reversible gates. Reversible decoder is designed using Fredkin gates with minimum Quantum cost.. The proposed method require less complexity, less hardware, minimum number of gates, minimum number of garbage inputs and minimum number of constant inputs than existing methods. The proposed circuits will be simulated using ModelSim simulator and implemented in Xilinx.

References

  1. R. Landauer, "Irreversibility and Heat Generation in the Computational Process", IBM Journal of Research and Development, 5, pp. 183- 191,1961.
  2. C.H. Bennett, "Logical Reversibility of Computation", IBM J.Researchand Development, pp. 525-532, November 1973.
  3. C H Bennett, "Notes on the History of Reversible Computation", IBM Journal of Research and Development,vol. 32, pp. 16-23, 1998.
  4. R. Feynman,"quantum mechanical computers:, Optic News, vol. 11,pp11-20, 1985.
  5. William C. Athas, Lars "J" ,Svensson, Jeffrey G. koller, NestorasTzartzanis, and Eric Ying – Chin Chou, "Low-power Digital Systemsbased on Adiabatic-Switching principle", IEEE Transactions on VLSIsystems, Vol. 2, No. 4, December 1994.
  6. A. Peres, "Reversible logic and quantum computers",phys.rev.A,Gen.Phys., vol. 32, no. 6, pp. 32663276, Dec. 1985.
  7. H.G Rangaraju, U. Venugopal, K.N. Muralidhara, K. B. Raja,"Lowpower reversible parallel binary adder/subtractor"arXiv.org/1009.6218,2010.
  8. J.M. Rabaey and M. Pedram, "Low Power Design Methodologies,"Kluwer Academic Publisher, 1997.
  9. T. Toffoli., "Reversible Computing", Tech memo MIT/LCS/TM-151,MIT Lab for Computer Science 1980.
  10. E. Fredkin and T. Toffoli, "Conservative logic," Int’l J.TheoreticalPhysics, Vol. 21, pp.219–253, 1982.
  11. Y. Syamala, and A. V. N. Tilak, "Reversible Arithmetic Logic Unit",Electronics Computer Technology (ICECT), 2011 3rd International, vol.5, pp.207-211,07 july 2011.
  12. Thapliyal H, Ranganathan N.," Design of Reversible Latches Optimizedfor Quantum Cost, Delay and Garbage Outputs" Centre for VLSI andEmbedded .
  13. V.Rajmohan, V.Ranganathan,"Design of counter using reversible logic"978-1-4244-8679-3/11/$26.00 ©2011 IEEE.
  14. Vivek V. Shende, Aditya K. Prasad, Igor L. Markov, and John P.Hayes," Synthesis of Reversible Logic Circuits", IEEE Transaction oncomputer-aided design of integrated circuits and systems, vol. 22, No. 6,June 2003.
  15. Payal Garg, Sandeep Saini,"A novel design of compact reversible SGgate and its applications",2014 14th International Symposium on Communications and Information Technologies(ISCIT), Sept 2014,pages 400-403, doi: 10.1109/ISCIT.2014.7011941
  16. Jadav Chandra as, Debashis De and Tapatosh Sadu." A novel low power nano scale reversible decoder using quantum dot cellular automata for nano communication", Third International Conferrence on devices, circuits and systems, 2016.

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Published

2018-07-30

Issue

Section

Research Articles

How to Cite

[1]
Y. Jyosthna, B. venkatesu, " Design and Implementation of ALU Using Reversible Decoder Logic, IInternational Journal of Scientific Research in Computer Science, Engineering and Information Technology(IJSRCSEIT), ISSN : 2456-3307, Volume 3, Issue 6, pp.280-287, July-August-2018.