Design and Implementation of Hamming Code with Error Correction Using Xilinx
DOI:
https://doi.org/10.32628/CSEIT24104117Keywords:
DSCH, Even parity, FPGA-Xilinx, Hamming code, VHDLAbstract
Advanced electrical circuits are very concerned about error-free communication. Information mistakes that happen during transmission may result in incorrect information being received. Error correction codes are frequently employed in electrical circuits to safeguard the data stored in memory and registers. One of these forward error correcting codes is the hamming code. It either employs the even parity or odd parity check approach. Here, we used the even parity check approach to implement hamming code. Compared to the parity check approach, hamming code is better. The hamming code is implemented here in Xilinx and uses a 7-bit data transmission scheme with 4 redundant bits. It is also used in the DSCH (Digital Schematic Editor & Simulator) programme. To find double bit errors, a specific parity bit is employed. For error detection and correction in this instance, we employed the SEDC-DED (Single Bit Error Detection and Correction-Double Bit Error Detection) method.
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