Machine Learning-Enhanced Greedy Algorithm for Optimizing Hold Time Violations in Advanced Node SoC Designs

Abstract

This article presents an innovative approach to resolving hold time violations in advanced technology nodes using a greedy algorithm methodology. The article addresses critical challenges in modern System-on-Chip (SoC) designs, particularly focusing on complex power domains and multiple clock regions. The proposed methodology revolutionizes traditional timing closure methods by implementing a systematic decision-making process that optimizes delay cell insertion while considering congestion, power consumption, and area utilization. Through advanced machine learning techniques, including transfer and active learning algorithms, the approach enables efficient identification of common points for hold fixing across multiple timing paths. The article demonstrates how this methodology significantly improves design closure efficiency in advanced FinFET and Gate-All-Around technologies while maintaining timing integrity across various operating conditions. The article also explores the implementation of congestion-aware optimization strategies and presents comprehensive analysis of the benefits in terms of power reduction, area optimization, and overall design closure efficiency in modern physical design workflows.