Design of 8T SRAM Cell Using Transmission Gates
DOI:
https://doi.org/10.32628/CSEIT25112727Keywords:
SRAM, System on Chips, transistors, latency, power, data stability, area, leakage currentAbstract
Around 70% of the power consumed and area occupied on a silicon die is due to SRAMs, which also take up about 70% of the total die space. This design provides a lower footprint, reduced latency, less expenditure of power, and increased data stability during read operations. System on Chips (SoCs) heavily relies on SRAMs, which usually take up about 70% of the total area of the die. This leaves room for potential expansion in the future. The usage of SRAMs has resulted in higher power demand, which can be addressed to the growth in the number of transistors and the associated leakage current that comes along with these transistors in smaller technologies.
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G. Chen, M. Fojtik, D. Kim, D. Fick, J. Park, M. Seok, M.-T. Chen, Z. Foo, D. Sylvester, and D. Blaauw, “Millimeter-scale nearly perpetual sensor system with stacked battery and solar cells,” in proc. of IEEE Int. Solid State Circuits Conf. Dig. Tech. Papers, Feb. 2010, pp. 288–289.
A.P.Chandrakasan, D.C.Daly, J.Kwong, and Y. K. Ramadass, “Next generation micro-power systems,” in proc. of IEEE Symp. VLSI Circuits, Jun. 2008, pp. 2–5.
Liang Wen, Xu Cheng, Keji Zhou, Shudong Tian, and Xiao yang Zeng, “Bit- Interleaving-Enabled 8T SRAM with Shared Data-Aware and Reference-Based Sense Amplifier”, IEEE Transactions on Circuits and Systems, vol. 63, No. 7, July 2016.
N. Maroof and B.-S. Kong, “10T SRAM using Half-VDD precharge and row-wise dynamically powered read port for low switching power and ultralow RBL leakage,” IEEE Trans. Very Large Scale Integr. (VLSI) Syst., vol. 25, no. 4, pp. 1193–1203, Apr. 2017.
J. P. Kulkarni and K. Roy, “Ultra low- voltage process-variation tolerant Schmitt- trigger-based SRAM design,” IEEE Trans. Very Large Scale Integr.(VLSI)Syst., vol. 20, no. 2, pp. 319–332, Feb. 2012.
M. Yamaoka, N. Maeda, Y. Shinozaki, Y. Shimazaki, K. Nii, S. Shimada, K. Yanagisawa, and T. Kawahara, “Low- power embedded SRAM modules with expanded margins for writing,” in proc. of IEEE Int. Solid-State Circuits Conf. Dig. Tech. Papers, Feb. 2005, pp. 480– 481.
T. H. Kim, J. Liu, and C.H. Kim,“ A voltage scalable 0.26 V, 64 kb 8T SRAM with Vmin lowering techniques and deep sleep mode,” IEEE J. Solid-State Circuits, vol. 44, no. 6, pp. 1785–1795, Jun. 2009.
N. Verma and A.P.Chandrakasan,“A256 kb 65 nm 8T sub-threshold SRAM employing sense-amplifier redundancy,” IEEE J.Solid-StateCircuits,vol.43,no.1, Pp.141–149, Jan 2008.
M. E. Sinangil, N. Verma, and A. P. Chandrakasan, “A reconfigurable 8T ultra- dynamic voltage scalable (U-DVS) SRAM in 65 nm CMOS,” IEEE J. Solid-State Circuits, vol.44, no.11, pp.3163–3173, Nov. 2009.
J. J. Wu, Y. H. Chen, M. F. Chang, P. W. Chou, C. Y. Chen, H. J. Liao, M. B. Chen, Y.H. Chu, W.-C. Wu, and H. Yamauchi, “A large VTH/VDD tolerant zigzag 8T SRAM with area-efficient decoupled differential sensing and fast write-back scheme,” IEEE J. Solid-State Circuits, vol.46, no.4, pp.815–827, Apr.2011.
J. P. Kulkarni, A. Goel, P. N Dai, and K. Roy, “A read-disturb-free, differential sensing 1R/1W port, 8T bit cell array,” IEEE Trans. Very Large Scale Integr. (VLSI)Syst., vol.19, no.9, pp.1727–1730,Sep. 2011.
M. H. Tu, J. Y. Lin, M. C. Tsai, S. J. Jou, and C. T. Chuang, “Single-ended sub- threshold SRAM with asymmetrical write/read-assist,” IEEE Trans. Circuits Syst. I, Reg. Papers, vol. 57, no. 12, pp. 3039– 3047, Dec. 2010.
Z. Liu and V. Kursun, “Characterization of a novel nine-transistor SRAM cell,” IEEE Trans. (VLSI) Syst., vol. 16, no. 4, pp.488–492, Apr.2008.
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