Multiple Error Detection and Correction in SRAM Emulated TCAMs Using RS Code

Abstract

Ternary Content Addressable Memories (TCAMs) are specialized types of memory primarily used in networking hardware, such as switches and routers, to perform high-speed operations. They are mainly utilized in hardware components designed for fast searching and matching operations. For example, TCAMs are used in intrusion detection and prevention systems (IDS/IPS) and network and packet processing in software defined system SDNs. TCAMs are used in application specific integrated circuits which are integrated into intellectual property blocks or as a standalone device. The FPGAs do not include any blocks for TCAMs. however, the flexibility of the FPGAs makes them dependable for implementation. The major issue caused while operating on TCAMs is soft errors which corrupt the stored bits. Memories can be protected using a parity bit which is an extra bit, needs an extra bit of memory or cyclic redundancy check used to verify data integrity by generating a checksum during data writing and comparing it during reading. The major drawback of using these methods is that these can only detect single bit error, to detect multiple bit errors we need error correcting codes (ECC). In this work Reed-Solomon code is used for correcting multiple bit errors.