Ramalinga Reddy Kotapati 2024. Advanced Clock Tree Synthesis Optimization: A Multi-Source Approach to Minimizing Skew and Power in Sub-7nm ASIC Designs. International Journal of Scientific Research in Computer Science, Engineering and Information Technology. 10, 6 (Dec. 2024), 2275–2283. DOI:https://doi.org/10.32628/CSEIT2410612440.