(1)
Ramalinga Reddy Kotapati. Advanced Clock Tree Synthesis Optimization: A Multi-Source Approach to Minimizing Skew and Power in Sub-7nm ASIC Designs. Int. J. Sci. Res. Comput. Sci. Eng. Inf. Technol 2024, 10 (6), 2275-2283. https://doi.org/10.32628/CSEIT2410612440.