RAMALINGA REDDY KOTAPATI. Advanced Clock Tree Synthesis Optimization: A Multi-Source Approach to Minimizing Skew and Power in Sub-7nm ASIC Designs. International Journal of Scientific Research in Computer Science, Engineering and Information Technology, [S. l.], v. 10, n. 6, p. 2275–2283, 2024. DOI: 10.32628/CSEIT2410612440. Disponível em: https://ijsrcseit.com/index.php/home/article/view/CSEIT2410612440. Acesso em: 12 jul. 2025.