Ramalinga Reddy Kotapati. “Advanced Clock Tree Synthesis Optimization: A Multi-Source Approach to Minimizing Skew and Power in Sub-7nm ASIC Designs”. International Journal of Scientific Research in Computer Science, Engineering and Information Technology, vol. 10, no. 6, Dec. 2024, pp. 2275-83, https://doi.org/10.32628/CSEIT2410612440.