Design of Reversible 32-Bit and 64-Bit BCD Add-Subtract using DKG Gate

Authors

  • Aseem Shrivastava  Trinity Institute of Technology & Research, Bhopal, Madhya Pradesh, India
  • Vipul Agarwal  Trinity Institute of Technology & Research, Bhopal, Madhya Pradesh, India

Keywords:

Reversible logic gates, ALU design, Reversible Arithmetic Logic unit (RALU), DKG Gate

Abstract

Reversible logic gates have gained great attention due to its competence to reduce the power dissipation. Therefore, it is widely adopted as the main requirement in low power digital design. Reversible logic has been widely used in advanced computing applications such as DNA computing, low power CMOS design, in bio information, Optical information processing, and nanotechnology and quantum computation. In all these applications the prime application of the Reversible logic is for designing and implementation of the Arithmetic and logic gate unit (ALU) tasks. This paper focuses to improve the efficiency of the arithmetic operations by reducing the desired power consumptions in the existing Reversible ALU designs and to compare the performance of the various existing reversible logic gates for ALU designs mentioned that ALU.

References

  1. Vivechana Dubey and Ravimohan Sairam, “An Arithmetic and Logic Unit Optimized for Area and power”, 978-1-4799-4910-6/14 $31.00 © 2014 IEEE DOI 10.1109/ACCT.2014.70.
  2. Mr. Abhishek Gupta, Mr. Utsav Malviya and Prof. Vinod Kapse, “Design of Speed, Energy and Power Efficient Reversible Logic Based Vedic ALU for Digital Processors”, 978-1-4799-4910-6/14 $31.00 © 2012 IEEE DOI 10.1109/ACCT.2014.70.
  3. Nidhi Gupta, “Thermal Analysis of Energy Efficient Clock Gated Arithmetic Logic Unit on FPGA”, 978-1-4799-4190-2/14/$31.00 ©2014 IEEE.
  4. Matthew Morrison and Nagarajan Ranganathan, “Design of a Reversible ALU based on Novel Programmable Reversible Logic Gate Structures”, 2013 IEEE Computer Society Annual Symposium on VLSI.
  5. LekshmiViswanath and Ponni.M, “Design and Analysis of 16 Bit Reversible ALU”, ISSN: 2278-0661 Volume 1, Issue 1 (May-June 2012), PP 46-53
  6. Akanksha Dixit and VinodKapse, “Arithmetic & Logic Unit (ALU) Design using Reversible Control Unit”, International Journal of Engineering and Innovative Technology (IJEIT) Volume 1, Issue 6, June 2012.
  7. Mr. Abhishek Gupta, Mr. UtsavMalviya and Prof. VinodKapse, “Design of Speed, Energy and Power Efficient Reversible Logic Based Vedic ALU for Digital Processors”, 2012 IEEE Computer Society Annual Symposium on VLSI.
  8. H. Thapliyal and N. Ranganathan, "A New Reversible Design of BCD
    Adder," To appear in Proc. Design Automation and Test in Europe (DATE), 2011.
  9. H. Thapliyal and N. Ranganathan, "Design of Reversible Sequential Circuits Optimizing Quantum Cost, Delay, and Garbage Outputs,"
    ACM Journal on Emerging Technologies in Computing Systems, 2010.
  10. H. Thapliyal and N. Ranganathan, "Reversible Logic Based Concurrently Testable Latches for Molecular QCA," IEEE Transactions on Nanotechnology, vol. 9, iss. 1, 2010, pp 62-69.
  11. M. Nachtigal, H. Thapliyal, and N. Ranganathan, "Design of a Reversible Single Precision Floating Point Multiplier Based on
    Operand Decomposition," To appear in Proc. Of 10th IEEE International Conference on Nanotechnology , 2010.
  12. M. K. Thomson, Robert Gluck and Holger Bock Axelsen, “Reversible Arithmetic Logic Unit for Quantum arithmetic”, Journal of Physics A: Mathematical and Theoretical. 43 (2010).
  13. H. R. Bhagyalakshmi, M. K. Venkatesha, “An improved design of a multiplier using reversible logic gates”, International Journal of Engineering Science and Technology, Vol. 2(8), pp: 3838-3845, 2010.
  14. Lihui Ni, Zhijin Guan, and Wenying Zhu, “A General Method of Constructing the Reversible Full-Adder”, Third International Symposium on Intelligent Information Technology and Security Informatics, pp.109-113, 2010.
  15. H. Thapliyal and N. Ranganathan, "Design of Efficient Reversible Binary Subtractors Based on A New Reversible Gate," Proc. of the
    IEEE Computer Society Annual Symposium on VLSI, 2009, pp 229-234.
  16. M.S. Islam, M.M. Rahman, Z. Begum and M.Z. Hafiz, “Low cost quantum realization of reversible multiplier circuit”, Information Technology Journal 8(2), pp: 208-213, 2009.

IInternational Journal of Scientific Research in Computer Science, Engineering and Information Technology

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Published

2017-08-31

Issue

Volume 2, Issue 4, July-August-2017

Section

Research Articles

License

Copyright (c) IJSRCSEIT

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This work is licensed under a Creative Commons Attribution 4.0 International License.

How to Cite

[1]
Aseem Shrivastava, Vipul Agarwal, " Design of Reversible 32-Bit and 64-Bit BCD Add-Subtract using DKG Gate, IInternational Journal of Scientific Research in Computer Science, Engineering and Information Technology(IJSRCSEIT), ISSN : 2456-3307, Volume 2, Issue 4, pp.387-395, July-August-2017.