Impact of Automation on the Test Insertion

Authors

  • Karthik C V  Assistant Professor, Department of ECE, New Horizon College of Engineering, Bangalore
  • Naveen H  Assistant Professor, Department of ECE, New Horizon College of Engineering, Bangalore
  • Rajiv Gopal  Assistant Professor, Department of ECE, New Horizon College of Engineering, Bangalore

Keywords:

Built in Self-Test, Design For Testability, Scan, Test Automation.

Abstract

In the present scenario, the transistor size (channel length) is diminishing which has led to number of irregularities and manufacturing defects. Thus the testing of the manufacturing defects in an IC is very important. In this paper, we are presenting the impact of the flow automation on the test insertion. We have performed the test insertion through an automated flow for 28nm and 16FF test cases.

References

  1. D.Vamsikrishna, Area analysis of 16 FinFET SRAMs” in National level Technical Symposium, Sri Shirdi Sai Engineering College, Bangalore.
  2. Laung-Terng Wang , Cheng-Wen Wu , Xiaoqing Wen, VLSI Test Principles and Architectures: Design for Testability (Systems on Silicon).
  3. Scan and ATPG Process Guide, Mentor graphics.
  4. FAST User Guide, LSI Internal Tool Guide.
  5. Jing Ye and et all, “Diagnosis and Layout Aware (DLA) Scan Chain Stitching” in IEEE Transactions on Very Large Scale Integration (VLSI) Systems, 2015 | Volume: 23, Issue: 3
  6. K. Katoh ; A. Doumar ; H. Ito, “Design of on-line testing for SoC with IEEE P1500 compliant cores using reconfigurable hardware and scan shift”, 11th IEEE International On-Line Testing Symposium, Year: 2005

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Published

2019-12-30

Issue

Section

Research Articles

How to Cite

[1]
Karthik C V, Naveen H, Rajiv Gopal, " Impact of Automation on the Test Insertion" International Journal of Scientific Research in Computer Science, Engineering and Information Technology(IJSRCSEIT), ISSN : 2456-3307, Volume 4, Issue 9, pp.532-535, November-December-2019.