Rapid Multiplier Architecture for Area and Power Optimization

Authors

  • Rajesh Gundlapalle  Department of Electronics and Communication Engineering, New Horizon College of Engineering, Bangalore, Karnataka, India
  • Sankarappa  Department of Electronics and Communication Engineering, Vemu Institute of Technology, Chittoor, A.P, India
  • Dr. Boda Saroja  Department of Electronics and Communication Engineering, Vemu Institute of Technology, Chittoor, A.P, India

Keywords:

Public-key cryptosystems, Elliptic Curve Cryptography (ECC) and RSA.

Abstract

The interest in unique devices has increased with the special development of low power, digital signal processing (DSP) systems used in mobile computers and portable multimedia applications. Multipliers plays a major role including its DSP program. Operator duplication is often used not only on DSP chips but also on many public key cryptosystems such as Elliptic Curve Cryptography (ECC) and RSA. The proposed 4-bit Vedic multiplier’s performance is analysed in terms of average power dissipation, delay, and also scaling effect of supply voltage.

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IInternational Journal of Scientific Research in Computer Science, Engineering and Information Technology

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Published

2020-09-30

Issue

Volume 4, Issue 11, September-2020

Section

Research Articles

License

Copyright (c) IJSRCSEIT

Creative Commons License

This work is licensed under a Creative Commons Attribution 4.0 International License.

How to Cite

[1]
Rajesh Gundlapalle, Sankarappa, Dr. Boda Saroja, " Rapid Multiplier Architecture for Area and Power Optimization" International Journal of Scientific Research in Computer Science, Engineering and Information Technology(IJSRCSEIT), ISSN : 2456-3307, Volume 4, Issue 11, pp.79-83, September-2020.